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AK4640_05 Datasheet, PDF (66/78 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ CODEC with MIC/HP/SPK-AMP | |||
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ASAHI KASEI
[AK4640]
2. When X'tal is used in PLL mode. (Master mode)
MCKPD bit
(Addr:01H, D7)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
PS1-0 bits
(Addr:04H, D5-4)
MCKO pin
BICK, LRCK
(Master Mode)
(1)
20ms(typ) (2)
40msec(max)
E xam p le :
A udio I/F Fo rm at : I2S
B IC K freq ue ncy at M a ste r M o de : 64fs
I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s te r C lo c k F re q ue n c y : 6 4 f s
(1 ) A d d r:0 1 H , D ata:4 0 H
(2 ) A d d r:0 1 H , D ata:6 0 H
(3)
00
XX
(4)
Output
(3 ) A d d r:0 4 H , D ata 6 A H
(4 ) M C K O , BIC K an d L R C K outpu t starts
Output
Figure 48. Clock Set Up Sequence(2)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = â1â â â0â and and power-up the Xâtal oscillator: PMXTL
bit = â0â â â1â
(2) Power-up PLL : PMPLL bit = â0â â â1â
The PLL should be powered-up after the Xâtal oscillator becomes stable. If X'tal and PLL are powered-up at
the same time, the PLL does not start. It takes Xâtal oscillator 20ms(typ) to be stable after PMXTL bit= â1â.
This time depends on Xâtal. PLL needs 40ms lock time the PMPLL bit = â0â â â1â.
(3) Enable MCKO output : MCKO bit = â0â â â1â and set up MCKO output frequency (PS1-0 bits)
(4) MCKO, BICK and LRCK are output after PLL lock time.
MS0273-E-02
- 66 -
2005/04
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