AK4640_05 Datasheet, PDF (47/78 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4640]
„ Register Definitions
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Power Management 1 PMVCM PMBPS PMBPM
0
PMMO PMAUX PMMIC PMADC
R/W
R/W
R/W
R/W
RD
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
PMADC: ADC Block Power Control
0: Power down (Default)
1: Power up
When the PMADC bit changes from “0” to “1”, the initialization cycle (2081/fs=47.2ms@44.1kHz) starts.
After initializing, digital data of the ADC is output.
PMMIC: MIC In Block Power Control
0: Power down (Default)
1: Power up
PMAUX: AUX In Power Control
0: Power down (Default)
1: Power up
PMMO: Mono Line Out Power Control
0: Power down (Default)
1: Power up
PMBPM: Mono BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPM= “0”, the path is still connected between BEEPM and HP/SPK-Amp. BPMHP and BPMSP
bits should be set to “0” to disconnect these paths, respectively.
PMBPS: Stereo BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPS= “0”, the path is still connected between BEEPL/R and HP/SPK-Amp. BPSHP and BPSSP
bits should be set to “0” to disconnect these paths, respectively.
PMVCM: VCOM Block Power Control
0: Power down (Default)
1: Power up
Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are
powered down.
When all bits except MCKPD bit are “0” in the 00H and 01H addresses, all blocks are powered down. The register
values remain unchanged. IPGA gain is reset when PMMIC bit is “0” (refer to the IPGA6-0 bits description).
When any of the blocks are powered up, the PMVCM bit must be set to “1”.
MCKI, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC=ALC2 bits = “0” or PDN pin
= “L”. The paths from BEEP to HP-Amp and SPK-Amp can operate without these clocks.
MS0273-E-02
- 47 -
2005/04