AK4640_05 Datasheet, PDF (16/78 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4640]
Parameter
Symbol
min
Control Interface Timing (4-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
tCCK
200
tCCKL
80
tCCKH
80
tCDS
40
tCDH
40
tCSW
150
tCSS
50
tCSH
50
tDCD
-
tCCZ
-
fSCL
-
Bus Free Time Between Transmissions
tBUF
4.7
Start Condition Hold Time (prior to first clock pulse) tHD:STA
4.0
Clock Low Time
tLOW
4.7
Clock High Time
tHIGH
4.0
Setup Time for Repeated Start Condition
tSU:STA
4.7
SDA Hold Time from SCL Falling
(Note 27) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.25
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
4.0
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Reset Timing
PDN Pulse Width
PMADC “↑” to SDTO valid
(Note 28)
tPD
150
(Note 29)
tPDV
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2081
Note 27. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 28. The AK4640 can be reset by the PDN pin = “L”.
Note 29. This is the count of LRCK “↑” from the PMADC bit = “1”.
max
Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
50
ns
70
ns
100
kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
1.0
µs
0.3
µs
-
µs
50
ns
-
ns
-
1/fs
MS0273-E-02
- 16 -
2005/04