AK4456 Datasheet, PDF (60/84 Pages) Asahi Kasei Microsystems – 115dB 768kHz Advanced 32-bit DAC

[AK4456]
(2) Reset Function (RSTN bit)
The DAC can be reset by setting RSTN bit to “0” but the internal registers are not initialized. In this time, the
corresponding analog outputs go to VREFH/2 and the DZF pin outputs “H” if clocks (MCLK, BICK and
LRCK) are input. Figure 60 shows an example of reset sequence by RSTN bit.
RSTN bit
Internal
RSTN bit
3~4/fs (6)
2~3/fs (5)
Internal
State
Normal Operation
Digital Block Power-down
Normal Operation
D/A In
(Digital)
D/A Out
(Analog)
“0” data
(1)
GD
(3) (2)
(3)
GD (1)
Clock In
BICK
Don’t care
DZF
2/fs(4)
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs are floating (Hi-Z) in power down mode.
(3) Small pop noise occurs at the edges(“ ”) of the internal timing of RSTN bit. This noise is output
even if “0” data is input.
(4) The DZF pin goes to “H” on the falling edge of RSTN bit and goes to “L” in 2/fs after a rising edge of
the internal RSTN.
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1”
to the internal RSTN bit “1”.
Figure 60. Reset Sequence Example 1
Note: When using both reset (RSTN bit = “0”) and DAC power-off bits (PW1-3 bits), power-off bits should be
set to “0” before RSTN bit.
015006886-E-00
- 60 -
2015/06