AK4456 Datasheet, PDF (21/84 Pages) Asahi Kasei Microsystems – 115dB 768kHz Advanced 32-bit DAC

[AK4456]
(Ta=-40  105C; AVDD=3.0  5.5V, TVDD=1.62  1.98V / 3.0  3.6V)
Parameter
Symbol Min. Typ. Max. Unit
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
nsec
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
tCCKL
80
nsec
tCCKH
80
nsec
tCDS
40
nsec
CDTI Hold Time
CSN “H” Time
CSN “” to CCLK “”
tCDH
40
nsec
tCSW
150
nsec
tCSS
50
nsec
CCLK “” to CSN “”
tCSH
50
nsec
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
- sec
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA 0.6
SDA Hold Time from SCL Falling
(Note 30) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO 0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Capacitive load on bus
Cb
-
- _sec
- _sec
-
sec
-
sec
-
sec
-
1.0
0.3
sec
sec
-
sec
50 ^nsec
400 ^pF
Power-down & Reset Timing
(Note 31)
PDN Accept Pulse Width
tAPD
150
nsec
PDN Reject Pulse Width
tRPD
30 nsec
Note 30. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 31.The AK4456 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L”
for more than 150ns for a certain reset. The AK4456 is not reset by the “L” pulse less than 30ns.
Note 32. I²C is a trademark of NXP B.V.
015006886-E-00
- 21 -
2015/06