AK4456 Datasheet, PDF (12/84 Pages) Asahi Kasei Microsystems – 115dB 768kHz Advanced 32-bit DAC

[AK4456]
(2) AVDD = 3.3V
(Ta=25°C: TVDD=3.3V, AVDD=3.3V: AVSS= DVSS=0V: VREFH1/2/3=AVDD, VREFL1/2/3= AVSS:
fs=44.1kHz: BICK=64fs: Signal Frequency=1kHz: 24-bit Input Data: R_L  2k: measurement bandwidth =
20Hz ~ 20kHz: External Circuit: (Figure 75), unless otherwise specified.)
Parameter
Min.
Typ.
Max. Unit
Resolution
32
bit
Dynamic Characteristics
(Note 9)
THD+N
fs=44.1kHz 0dBFS
BW=20kHz 60dBFS
-
-93
-86
dB
-
-48
-
dB
fs=96kHz 0dBFS
-
-92
-
dB
BW=40kHz 60dBFS
-
-45
-
dB
fs=192kHz 0dBFS
-92
-
dB
BW=40kHz 60dBFS
-45
-
dB
BW=80kHz 60dBFS
-41
-
dB
Dynamic Range(60dBFS with A-weighted) (Note 10)
106
111
-
dB
S/N (A-weighted)
(Note 11)
106
111
-
dB
Inter channel Isolation (1kHz)
100
110
-
dB
DC Accuracy
Inter channel Gain Mismatch
0
0.3
dB
Gain Drift
(Note 12)
-
20
-
ppm/°C
Output Voltage
(Note 13)
1.66 1.85 2.04 Vpp
Load Resistance
(Note 14)
2
k
Load Capacitance
(Note 14)
30
pF
Power Supplies
Power Supply Current
Normal operation
(PDN pin = “H”)
AVDD
TVDD (fs = 44.1kHz)
TVDD (fs = 96kHz)
TVDD (fs = 192kHz)
-
-
-
-
18
6
10
16
mA
mA
mA
mA
Power down (PDN pin = “L”)
(Note 15)
AVDD+TVDD
1
100
A
Note 9. Measured by Audio Precision, System Two. Averaging mode.
Note 10. Figure 75 External LPF Circuit Example 1. 100dB for 16-bit data.
Note 11. Figure 75 External LPF Circuit Example 1. S/N does not depend on input data size.
Note 12. The voltage on (VREFH1/2/3  VREFL1/2/3) is held +5V externally.
Note 13. The full scale voltage when applying a 1kHz sine wave (0dB) in PCM mode, or when applying a
1kHz sine wave (25~75% duty) in DSD mode. Output voltage scales with the voltage of
(VREFH1/2/3  VREFL1/2/3).
DAC1: AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFH1  VREFL1)/5
DAC2: AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFH2  VREFL2)/5
DAC3: AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFH3  VREFL3)/5
Note 14. Regarding Load Resistance, AC load is 2k (min) with a DC cut capacitor (Figure 75). DC load is 3.5
k (min) without a DC cut capacitor (Figure 75). The load resistance value is with respect to ground.
Analog characteristics are sensitive to capacitive load that is connected to the output pin. Therefore
the capacitive load must be minimized.
Note 15. In the power down mode. All other digital input pins including clock pins (MCLK, BICK and LRCK)
are held DVSS.
015006886-E-00
- 12 -
2015/06