AK4456 Datasheet, PDF (52/84 Pages) Asahi Kasei Microsystems – 115dB 768kHz Advanced 32-bit DAC

[AK4456]
■ Zero Detection (PCM mode, DSD mode)
When zero detection function is enabled, the DZF pin goes to “H” if the input data at each channel is
continuously zeros for 8192 LRCK cycles. Zero detection channels (AOUTL1-3N/P and AOUTR1-3N/P pins)
can be selected by 07H/08H registers (L1-3 bits, R1-3 bits). The DZF pin immediately returns to “L” if the
input data of each channel is not zero. If the RSTN bit is “0”, the DZF pins of both channels go to “H”. The
DZF pin of both channels go to “L” after 4 ~ 5/fs when RSTN bit returns to “1”. The DZFB bit can invert the
polarity of the DZF pin. If all channels are disabled, the DZF pin outputs “Not zero”. Zero detection function is
disabled when DSDD bit = “1”.
DZFB bit
Data
DZF pin
0
Not zero
Zero detect
L
H
1
Not zero
Zero detect
H
L
Not zero: One of the zero detection channels set by L1-3 bits and R1-3 bits does not detect zero.
Zero detect: All zero detection channels set by L1-3 bits and R1-3 bits detect zero.
Table 20. DZF Pin Function
■ LR Channel Output Signal Select (PCM mode, DSD mode)
Input and output signal combination of AOUTL1-3 and AOUTR1-3 pins can be set by MONO1-3 bits and
SELLR1-3 bits. The output signal phase of DAC is controlled by INVL1-3 and INVR1-3 bits. With these
settings, sixteen patterns of signal combinations are available for DAC1-3. These settings are available for any
audio format.
MONO1 bit
0
0
1
1
SELLR1 bit
0
1
0
1
INVL1 bit
INVR1 bit
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
Table 21 Output Select for DAC1
L1ch Out
L1ch In
L1ch In Invert
L1ch In
L1ch In Invert
R1ch In
R1ch In Invert
R1ch In
R1ch In Invert
L1ch In
L1ch In Invert
L1ch In
L1ch In Invert
R1ch In
R1ch In Invert
R1ch In
R1ch In Invert
R1ch Out
R1ch In
R1ch In
R1ch In Invert
R1ch In Invert
L1ch In
L1ch In
L1ch In Invert
L1ch In Invert
L1ch In
L1ch In
L1ch In Invert
L1ch In Invert
R1ch In
R1ch In
R1ch In Invert
R1ch In Invert
015006886-E-00
- 52 -
2015/06