AK4115 Datasheet, PDF (48/64 Pages) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio Interface Transceiver

ASAHI KASEI
[AK4115]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
•
23H
24H
•
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
Register Name
CLK & Power Down Control
Format & De-em Control
Input/ Output Control 0
Input/ Output Control 1
INT0 MASK
INT1 MASK
DAT Mask & DTS Detect
Receiver Status 0
Receiver Status 1
Receiver Status 2
Clock Control
TX Control
RX Channel Status Byte 0
•
RX Channel Status Byte 23
TX Channel Status Byte 0
•
TX Channel Status Byte 23
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
Optional Control
D7
CS12
AES3
TX1E
EFH1
MQIT0
MQIT1
DIV
QINT
FS3
0
TX1NE
MSEL
CR7
•
CR191
CT7
•
CT191
PC7
PC15
PD7
PD15
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
0
D6
D5
D4
D3
D2
D1
D0
BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN
DIF2 DIF1 DIF0 DEAU DEM1 DEM0 ACKS
OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00
EFH0 UDIT BCU_IO DIT IPS2 IPS1 IPS0
MAUT0 MCIT0 MULK0 MV0 MSTC0 MAUD0 MPAR0
MAUT1 MCIT1 MULK1 MV1 MSTC1 MAUD1 MPAR1
XMCK FAST DCNT DTS16 DTS14 MDAT1 MDAT0
AUTO CINT UNLCK VRX STC AUDION PAR
FS2 FS1 FS0 PEM DAT DTSCD NPCM
0
0
0
0
0
QCRC CCRC
0 MCK2E MCK1E ASYNC WSYNC XSEL PSEL
ECKS1 ECKS0 EDIF1 EDIF0 CTRAN CCRE VTX
CR6 CR5 CR4 CR3 CR2 CR1 CR0
•
•
•
•
•
•
•
CR190 CR189 CR188 CR187 CR186 CR185 CR184
CT6
CT5
CT4
CT3 CT2
CT1
CT0
•
•
•
•
•
•
•
CT190 CT189 CT188 CT187 CT186 CT185 CT184
PC6 PC5 PC4 PC3 PC2 PC1 PC0
PC14 PC13 PC12 PC11 PC10 PC9 PC8
PD6 PD5 PD4 PD3 PD2 PD1 PD0
PD14 PD13 PD12 PD11 PD10 PD9 PD8
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q16
Q15
Q14
Q13 Q12
Q11
Q10
Q24 Q23 Q22 Q21 Q20 Q19 Q18
Q32 Q31 Q30 Q29 Q28 Q27 Q26
Q40 Q39 Q38 Q37 Q36 Q35 Q34
Q48 Q47 Q46 Q45 Q44 Q43 Q42
Q56 Q55 Q54 Q53 Q52 Q51 Q50
Q64 Q63 Q62 Q61 Q60 Q59 Q58
Q72 Q71 Q70 Q69 Q68 Q67 Q66
Q80 Q79 Q78 Q77 Q76 Q75 Q74
0
0
0
0
0
CTX
0
Notes:
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
Data must not be written to addresses 4BH through FFH.
MS0573-E-00
- 48 -
2006/12