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AK4115 Datasheet, PDF (39/64 Pages) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio Interface Transceiver | |||
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ASAHI KASEI
[AK4115]
 Error Handing for ELRCK (PSEL = â1â)
The followings two events cause the INT0 and INT1 pins to show the status of the interrupt conditions. When the PLL is
OFF (Clock Operation Mode 1), the INT0 and INT1 pins go to âLâ.
1. UNLCK : PLL unlock state detect
â1â when the PLL loses lock.
The AK4115 loses lock when the phase difference between the current ELRCK and the previous
ELRCK is more than 5% after â4 x fsâ.
The PLL is locked when the phase difference between the current ELRCK and the pervious
ELRCK is less than 2% after â256 x fsâ.
When the PLL loses lock, the PLL goes to a free running state. The sampling frequency is
typically 11kHz in this case.
2. FS3-0
: Sampling frequency detection
FS3-0 bits are updated every â128 x fsâ. When FS3-0 bits are changed, the STC bit is not changed
and the INT0 and INT1 pins go to âHâ after â1 x fsâ
In this mode, INT0 does not have the hold function. Therefore, INT0 and INT1 go to âLâ at the same time when those
events are removed. Each INT0/1 pins can mask those two events individually.
1. Parallel Mode
In parallel mode, INT0 triggers UNLCK, and INT1 triggers when FS3-0 bits are changed. INT0 and INT1 go âLâ after
each event is removed.
2. Serial Mode
In serial mode, INT1 and INT0 outputs an ORed signal based on the two interrupt events shown above. When masked,
the interrupt event does not affect operation of the INT1-0.
UNLCK
1
0
Event
Pin
Change of FS3-0 bits
SDTO
x
âLâ
1
Output
Table 27. Error Handling (x: Donât care)
TX
Output
Output
MS0573-E-00
- 39 -
2006/12
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