AK4115 Datasheet, PDF (19/64 Pages) Asahi Kasei Microsystems – High Feature 192kHz 24bit Digital Audio Interface Transceiver

ASAHI KASEI
[AK4115]
2. Asynchronous Mode: ASYNC bit = “1”, PSEL = “0”
When ASYNC bit is “1”, DIT and DIR can operate at different sample rates(non-multiples). In Mode1, Mode2 (When
the PLL is the unlock state) and Mode3, SDTO is fixed “L”. The input timing of DAUX should be synchronized with
ELRCK and EBCIK. The master clock of TX can be selected to either X’tal or EMCK by the MSEL bit (See Table 4).
MSEL bit Master Clock
0
X’tal
Defalut
1
EMCK
Table 4. Master clock setting for TX in asynchronous mode.
Mode
CM1 CM0
UNLOCK
PLL
Status
X'tal
Status
Clock
Source
RX
Clock
I/O
SDTO
TX
Clock
Source
Clock
I/O
0
0
0
X’tal
-
ON
ON
(Note 19)
PLL
(RX)
Note 20
RX
or
EMCK
Note 21
(Note 22)
1
0
1
X’tal
-
OFF
ON
X'tal Note 20 “L”
or
Note 21
EMCK
2
1
0
0
ON
ON
PLL
(RX)
Note 20
RX
X’tal
or
EMCK
Note 21
X’tal
1
ON
ON
X'tal Note 20 “L”
or
Note 21
EMCK
X’tal
3
1
1
-
ON
ON
X'tal Note 20 “L”
or
Note 21
EMCK
Note 18. ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note 19 When the X’tal is not used as clock comparison for sampling frequency detection (i.e. XTL1,0 = “1,1”), the
X’tal is OFF.
Note 20: MCKO1/2, BICK, LRCK
Note 21. EMCK or X’tal, EBICK, ELRCK, DAUX
Note 22. When X’tal is OFF, the clock source supports EMCK only.
Table 5. Clock operation for DIT/DIR in asynchronous mode
XTI1
XTO1
ACKS ^XTI2
XTO2
X'tal
Oscillator
XSEL
X'tal
Oscillator
RXP0
RXN0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
TX0
TXP1
TXN1
MS0573-E-00
8 to 3
Input
Selector
Clock
Recovery
DAIF
Decoder
Clock Selector
(CM1-0)
DEM
“L”
Clock
Generator
Audio I/F
for RX
MSEL
Audio I/F
for TX
DIT
Figure 16. Clocks for DIT/DIR in asynchronous mode
- 19 -
MCKO1
MCKO2
LRCK
BICK
SDTO
EMCK
ELRCK
EBICK
DAUX
2006/12