AK4618 Datasheet, PDF (44/60 Pages) Asahi Kasei Microsystems – 192kHz 24-bit 6ch/12ch Audio CODEC with Microphone Interface

[AK4618]
■ Reset Function
When RSTN bit= “0”, the analog and digital part of ADC and DACs are powered-down, but the internal register are not
initialized. The analog outputs go to Hi-Z, the SDTO pin goes to “L”. As some click noise occurs, the analog output
should be muted externally if the click noise influences system application. Figure 38 shows the power-up sequence.
RSTN bit
Internal
RSTN bit
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
4~5/fs (8)
3~4/fs (9)
(1)
Normal Operation
Power-down
Init Cycle
(2)
Normal Operation
Normal Operation
Digital Block Power-down _{Init Cycle}
GD ⁽³⁾
Normal Operation
GD
(4)
“0”data
“0”data
(3)
GD
(7) (6)
(7)
(7)
(5)
GD
Clock In
MCLK,LRCK,BICK
Don’t care
Notes:
(1) The analog section of the ADC is initialized after exiting reset state.
The initializing cycle is 1056fs. When start-up the AK4618, ADC input voltage should be operating common
voltage.
(2) The analog section of DAC is initialized after exiting exiting reset state.
(3) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group
delay (GD).
(4) ADC output is “0” data at power-down state.
(5) Click noise occurs when the initializing cycle is finished. Mute the digital output externally if the click noise
influences system application.
(6) The analog outputs go to Hi-Z when RSTN bit becomes “0”.
(7) Click noise occurs at 45/fs after RSTN bit becomes “0”, and it occurs at 34/fs after RSTN bit becomes “1”.
(8) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
(9) There is a delay, 3~4/fs from RSTN bit “1” to the start of initial cycle.
Figure 38. Reset Sequence Example
015000617-E-00
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2015/01