AK4618 Datasheet, PDF (42/60 Pages) Asahi Kasei Microsystems – 192kHz 24-bit 6ch/12ch Audio CODEC with Microphone Interface

[AK4618]
■ Power-Down
All ADCs and DACs of the AK4618 are placed in power-down mode by bringing the PDN pin “L” which resets both
digital filters at the same time. The PDN pin “L” also resets the control registers to their default values. In power-down
mode, the SDTO goes to “L”, and the analog outputs go to Hi-Z. This reset should always be executed after power-up. For
the ADC, an analog initialization cycle (1056/fs) starts 3~4/fs after exiting power-down mode. The output data, SDTO is
available after 1059~1060 cycles of the LRCK clock. For the DAC, an analog initialization cycle (516/fs) starts 3~4/fs
after exiting power-down mode. The analog outputs go to Hi-Z during the initialization. Figure 36 shows the power-down
and power-up sequences.
AVDD1/AVD
D2/DVDD
(11)
PDN
VCOM
150ns
REGO
(9)
3~4/fs
Internal PDN
(10)
1056/fs ⁽¹⁾
ADC Internal
State
DAC Internal
State
Init Cycle
516/fs ⁽²⁾
Init Cycle
ADC In
(Analog)
Normal Operation
Power-down
Normal Operation
GD ⁽³⁾
Power-down
GD
ADC Out
“0”data (4)
(6)
(Digital)
“0”data
DAC In
(Digital)
“0”data
DAC Out
(5)
(Analog)
Clock In
MCLK,LRCK,BICK
Don’t care
GD(3)
(7)
“0”data
GD
(7)
(7)
Don’t care
External
Mute
Mute ON (8)
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting internal power-down state.
When start-up the AK4618, ADC input voltage should be operating common voltage.
It is necessary to wait for the charge up time of HPF which consists of analog inputs.
When the external capacitor is 1uF and the input impedance is 60kΩ(typ), τ = 0.06 sec.
(2) The analog part of DAC is initialized after exiting internal power-down state.
(3) Digital output corresponds to analog input and analog output corresponds to digital input have group delay (GD).
(4) ADC output is “0” data at power-down state.
(5) The analog outputs go to Hi-Z in power-down mode.
(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system applications.
(7) Click noise occurs at the falling edge of PDN and at 519~520/fs after exiting internal power-down state.
(8) Mute the analog output externally if the click noise (7) influences system applications.
(9) There is a delay, 3~4/fs from internal power up to the start of initial cycle.
(10) The PDN pin must be “L” when power up the AK4618 and set to “H” after all poweres are supplied.
(11) The internal power-down state is released when MCLK counter rise.Do not write to the registers for
32768/MCLK(2.67ms@MCLK=12.288MHz, until internal power down is released after the PDN pin = “H”.
Figure 36. Pin power-down/Pin power-up sequence example
015000617-E-00
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2015/01