AK4618 Datasheet, PDF (43/60 Pages) Asahi Kasei Microsystems – 192kHz 24-bit 6ch/12ch Audio CODEC with Microphone Interface

[AK4618]
All ADCs and all DACs can be powered-down individually through the PMADC bits and PMDAC bits. DAC1-6 can be
power-down individually by PMDA6-1 bits. In this case, the internal register values are not initialized. When PMADC bit
= “0”, SDTO goes to “L”. When PMDAC bit = “0”, the analog outputs go to Hi-Z. As some click noise occurs, the analog
output should be muted externally if the click noise influences system applications. Figure 37 shows the power-down and
power-up sequences.
PMADC/PMDAC bit
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,BICK
External
Mute
4~5/fs (9)
3~4/fs (10)
(1)
Normal Operation
Power-down
Normal Operation
GD ⁽³⁾
Power-down
Init Cycle
516/fs ⁽²⁾
Init Cycle
Normal Operation
Normal Operation
GD
(4)
“0”data
“0”data
(3)
GD
(7)
(5)
(6)
GD
(7)
Don’t care
(8)
Mute ON
Notes:
(1) The analog section of ADC is initialized after exiting power-down state.
(2) The analog section of DAC is initialized after exiting power-down state.
(3) Digital output corresponding to the analog inputs and analog outputs corresponding to the digital inputs have group
delay (GD).
(4) ADC output is “0” data at power-down state.
(5) DAC output is Hi-Z in power-down state.
(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise
influences system application.
(7) Click noise occurs at 45/fs after PMDAC bit becomes “0”, and occurs at 519520/fs after PMDAC bit becomes
“1”.
(8) Mute the analog output externally if the click noise (7) influences system application.
(9) There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable ADC power-down.
There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable DAC power-down.
(10) There is a delay, 3~4/fs from PMADC and PMDAC bits become “1” to the start of initial cycle.
Figure 37. Bit power-down/Bit power-up sequence example
015000617-E-00
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2015/01