AK4618 Datasheet, PDF (17/60 Pages) Asahi Kasei Microsystems – 192kHz 24-bit 6ch/12ch Audio CODEC with Microphone Interface

[AK4618]
Parameter
Symbol Min.
Typ.
Max. Unit
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
-
s
Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6
-
s
Clock Low Time
tLOW
1.3
-
s
Clock High Time
tHIGH
0.6
-
s
Setup Time for Repeated Start Condition
tSU:STA 0.6
-
s
SDA Hold Time from SCL Falling
(Note 18) tHD:DAT 0
-
s
SDA Setup Time from SCL Rising
tSU:DAT 0.1
-
s
Rise Time of Both SDA and SCL Lines
tR
-
1.0 s
Fall Time of Both SDA and SCL Lines
tF
-
0.3 s
Setup Time for Stop Condition
tSU:STO 0.6
-
s
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Capacitive load on bus
Cb
-
50 ns
400 ^pF
Power-down & Reset Timing
PDN Pulse Width
(Note 19) tPD
150
ns
PDN “” to SDTO valid
(Note 20) tPDV
32768/MCLK
1/fs
+1059/fs
Note 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 19. The AK4618 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” for more
than 150ns for a certain reset. The AK4618 is not reset by the “L” pulse less than 30ns.
Note 20. These cycles are the numbers of MCLK and LRCK rising from the PDN pin rising.
Note 21. I²C-bus is a trademark of NXP B.V.
015000617-E-00
- 17 -
2015/01