AK4560A Datasheet, PDF (42/47 Pages) Asahi Kasei Microsystems – 16bit CODEC with ALC and MIC/HP/SPK-Amps

ASAHI KASEI
[AK4560A]
(1) Recovery waiting counter reset level (LMTH) or reference value of recovery operation (REF6-0)
Zero crossing detect
Gain Level (RATT)
Limiter detection level (LMTH)
(2) Zero crossing timeout (ZTM1-0) & Recovery waiting time (WTM1-0)
Figure 33. The continuous ALC1 Recovery Operation
(1). When the input signal exceeds the ALC1 recovery waiting counter reset level, the ALC1 recovery operation stops, the
ALC1 recovery operation is repeated when input signal level is below “LMTH” again. When the IPGA value by
repeating the ALC1 recovery operation reaches the reference level (REF6-0 bits), the ALC1 recovery operation stops
also
(2). ZTM bit sets zero crossing timeout and WTM bit sets the ALC1 recovery operation period. When the ALC1 recovery
waiting time (WTM1-0 bits) is shorter than zero crossing timeout period of ZTM1-0 bit, the ALC1 recovery is
operated by the zero crossing timeout period of ZTM1-0 bit. Therefore, in this case the auto recovery operation period
is not constant.
3. ALC1 Operation OFF (ALC1 bit = “0”)
The zero crossing detection of IPGA is done to L/R channels independently. Zero crossing timeout is set by ZTM1-0 bits.
When the control register is written from uP, the zero crossing counter for L/R channels commonly is reset and its counter
starts. When the signal detects zero crossing or zero crossing timeout, the written value from uP becomes a valid for the
first time. In case of writing to the control register continually, the control register should be written by an interval more
than zero crossing timeout. If an appointed interval is written, there is possible to the different value the IPGA value of
L/R channels
For example, when the present IPGA value is updated by zero crossing detection in a channel of one side and other
channel is not updated, if the new data is written in IPGA, the updated channel is keeping the last IPGA value and other
channel is updated to a new IPGA value by the last zero crossing counter. Therefore, zero crossing counter does not reset
when the zero crossing detection is waiting.
MS0028-E-00
- 42 -
2000/05