AK4560A Datasheet, PDF (16/47 Pages) Asahi Kasei Microsystems – 16bit CODEC with ALC and MIC/HP/SPK-Amps

ASAHI KASEI
[AK4560A]
n Audio Interface Format
Data is shifted in/out the SDTI/SDTO pins using BCLK and LRCK inputs. The serial data is MSB-first, 2's compliment
format, ADC is MSB justified and DAC is LSB justified.
LRCK
01
BCLK(32fs)
23
89
10 11 12 13 14 15 0 1
23
89
10 11 12 13 14 15 0 1
SDTO(o)
SDTI(i)
15 14 13 8 7 6 5 4 3 2 1 0 15 14 13 8 7 6 5 4 3 2 1 0 15
0 1 23
BCLK(64fs)
14 15 16 17 18
31 0 1 2 3
14 15 16 17 18
31 0 1
SDTO(o)
15 14 13 13 2 1 0
15 14 13 1 2 1 0
15
SDTI(i)
Don’t Care
15 14
15:MSB, 0:LSB
Lch Data
10
Don’t Care
15 14
Rch Data
10
Figure 8. Audio Data Timing
n Control Register Timing
The data on the 3-wire serial interface consists of op-code (3bit), address (LSB-first, 5bit) and control data (LSB-first,
8bit). The Transmitting data is output to each bit by “↓” of CCLK, the receiving data is latched by “↑” of CCLK. Writing
data becomes effective by “↑” of CS . Reading data becomes Hi-z (floating) by “↑” of CS . CS should be held to “H”
at no access.
CCLK always need 16 edges of “↑” during CS . Reading/Writing of the address except 00H∼09H are inhibited.
Reading/Writing of the control registers by except op1-0 = “11” are invalid.
In case of reading data, nothing is written to D0∼D7 data.
CS
CCLK
CDTIO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
op0 op1op2 A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7
"1" "1" "X"
op0-op2: Op-code (111:WRITE, 110:READ)
A0-A4: Address
D0-D7: Control Data
Figure 9. Control Data Timing
MS0028-E-00
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2000/05