AK4560A Datasheet, PDF (19/47 Pages) Asahi Kasei Microsystems – 16bit CODEC with ALC and MIC/HP/SPK-Amps

ASAHI KASEI
[AK4560A]
Power Management Control
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H Power Management Control LOUTP SPKP HPP VCOM DAC ADC IPGA MIC
R/W
R/W
RESET
1
1
1
1
1
1
1
1
MIC: MIC Block (Pre-Amp, EQ-Amp, HPF-Amp and MPWR) Power Control.
0: OFF. Output pins are Hi-z.
1: ON (RESET)
IPGA: IPGA (ALC1) Power Control
0: OFF
1: ON (RESET)
ADC: ADC Power Control
0: OFF. SDTO pin is output “L”.
1: ON (RESET)
When ADC bit changes from “0” to “1”, initializing cycle (8224/fs=171.3ms@fs=48kHz) starts.
After initializing cycle, digital data of ADC is output.
DAC: DAC Power Control
0: OFF
1: ON (RESET)
VCOM: Common Voltage (VCOM, HVCM and MVCM) Power Control
0: OFF
1: ON (RESET)
HPP: Headphone-Amp Power Control (Including OPGA, BEEP and HP-Amp)
0: OFF. Output of Headphone-Amp becomes “L” (AGND).
1: ON (RESET)
SPKP: Speaker Block Power Control (Including OPGA, BEEP, MOUT, ALC2 and Speaker-Amp)
0: OFF. Output of Speaker-Amp is Hi-z.
1: ON (RESET)
LOUTP: Lineout Power Control
0: OFF. Output pin is Hi-z.
1: ON (RESET)
Analog volume (OPGA) are enabled when SPKP bit = “1” or HPP bit = “1”.
These bits can be partially powered-down by ON/OFF (“1” / “0”). When PD pin goes
“L”, all the circuit in AK4560A can be powered-down regardless of these bits in the
address.
When bit in this address goes all “0”, all the circuits in AK4560A can be also powered-
down. But contents of registers are kept.
When each block is operated, VCOM bit must go “1”. VCOM bit can write “0” when all
bits in this address can be “0”.
Except the case of IPGA=ADC=DAC=SPKP=HPP= “0” or PD pin = “L”, MCLK,
BCLK and LRCK should not be stopped.
MS0028-E-00
- 19 -
2000/05