AK4560A Datasheet, PDF (12/47 Pages) Asahi Kasei Microsystems – 16bit CODEC with ALC and MIC/HP/SPK-Amps

ASAHI KASEI
DC CHARACTERISTICS
(Ta=25°C; VA=VD=2.6 ∼ 3.3V)
Parameter
Symbol
min
typ
High-Level Input Voltage
VIH
1.5
-
Low-Level Input Voltage
VIL
-
-
High-Level Output Voltage Iout=-200uA
VOH
VD-0.2
-
Low-Level Output Voltage Iout=200uA
VOL
-
-
Input Leakage Current
Iin
-
-
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=VD=2.6 ∼ 3.3V; C_L=20pF)
Parameter
Symbol
min
Control Clock Frequency
Master Clock(MCLK) 256fs: Frequency
fCLK
2.048
Pulse Width Low
Pulse Width High
384fs: Frequency
tCLKL
tCLKH
fCLK
28
28
3.072
Pulse Width Low
tCLKL
23
Pulse Width High
tCLKH
23
Channel Select Clock (LRCK): Frequency
Duty
fs
8
Duty
45
Audio Interface Timing
BCLK Period
BCLK Pulse Width Low
Pulse Width High
LRCK Edge to BCLK “↑” (Note 33)
BCLK “↑” to LRCK Edge (Note 33)
tBLK
tBLKL
tBLKH
tLRB
tBLR
312.5
130
130
50
50
LRCK to SDTO(MSB) Delay Time
BCLK “↓” to SDTO Delay Time
SDTI Latch Hold Time
SDTI Latch Set up Time
tLRM
tBSD
tSDH
50
tSDS
50
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
Pulse Width High
tCCKL
80
tCCKH
80
CDTIO Latch Set Up Time
tCDS
50
CDTIO Latch Hold Time
tCDH
50
CSN “H” Time
tCSW
150
CSN ”↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
CDTIO Output Delay Time
tDCD
CSN “↑” to CDTO(Hi-Z) Time (Note 34)
tCCZ
Reset Timing
PD Pulse Width
tPDW
150
PD “↑” to SDTO Delay Time
tPDV
Note 33. BCLK rising edge must not occur at the same time as LRCK edge.
Note 34. RL=1kΩ/10% Change. (Pull-up operates for VD)
typ
12.288
18.432
48
50
8224
[AK4560A]
max
Units
-
V
0.6
V
-
V
0.2
V
±10
uA
max
Units
12.8
MHz
ns
ns
19.2
MHz
ns
ns
50
kHz
55
%
ns
ns
ns
ns
ns
80
ns
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
ns
70
ns
ns
1/fs
MS0028-E-00
- 12 -
2000/05