AK4560A Datasheet, PDF (37/47 Pages) Asahi Kasei Microsystems – 16bit CODEC with ALC and MIC/HP/SPK-Amps

ASAHI KASEI
[AK4560A]
SPPS
-
+
SPPS
or
SPKP
SP0
SPPS
8Ω
SPPS
-
+
SPPS
SPPS
SPKP
SP1
R1
Figure 28. Speaker-Amp Power-Down-Mode
1. Monaural Output
Both L/R channels of output signal from analog volume (OPGA) are mixed at (L+R)/2. When MOUT bit is “0”, these
signals can be OFF. Then MOUT pin outputs VCOM voltage. Load impedance is 10kΩ (min.).
When SPKP bit is “0”, MOUT pin becomes Power-Down-Mode and outputs Hi-z.
2. ALC2
Input resistance of ALC2 is 23kΩ (typ.) and centered around VCOM voltage, and input signal level is –5.5dBV. (Refer to
Figure 29)
Limiter detection level is not related to power supply voltage, output level is limited by the ALC2 circuit when input
signal exceeds –7.5dBV (=FS-2dB@VA=2.8V) and over.
When the continuous signal of –7.5dBV and over is input to the ALC2 circuit, the change period of ALC2 limiter
operation is 2/fs=42us@fs=48kHz and the attenuation level is 0.5dB/step.
The ALC2 recovery operation is always detected by zero crossing operation and gains 1dB/step. The ALC2 recovery
operation is done until input level of speaker-Amp goes to –9.5dBV(=FS-4dB@VA=2.8V). The ALC2 recovery
operation period is fixed to 2048/fs=42.7mS@fs=48kHz.
In case of inputting signal between –7.5dBV and –9.5dBV, the ALC2 limiter or recovery operations are not done.
When PD pin changes from “L” to “H” or SPKP bit changes from “0” to “1”, the initilizing cycle (2048/fs = 42.7ms
@fs=48kHz) starts. ALC2 is disabled during initilizing cycle, ALC2 starts after finishing the initilizing cycle.
Parameter
Operation Start Level
Period
fs=48kHz
fs=32kHz
Zero-crossing Detection
ATT/GAIN
ALC2 Limiter operation
-7.5dBV
2/fs = 42us
2/fs = 63us
No
0.5dB step
Table 16. Content of ALC2
ALC2 Recovery operation
-9.5dBV
2048/fs = 42.7ms
2048/fs = 64ms
Yes(Timeout = 2048/fs )
1dB step
MS0028-E-00
- 37 -
2000/05