AK8825 Datasheet, PDF (40/162 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

■ On chip out-put limiter
[AK8825]
Limiter function is performed on signals which exceed Pedestal Level.
Limiter Levels are set at “no limiter”, “- 1.5IRE”, “- 7IRE”.
The limit level is set with HDCLPLVL[1:0]-bit of HD VBI & Clip Level Control Register (R/W) [Sub Address 0x01] in
Component Video Encoder mode and SDCLPLVL[1:0]-bit of SD Block Delay Register (R/W) [Sub Address 0x13] in Composite
Video Encoder mode.
HD VBI & Clip Level Control Register
Sub Address 0x01
bit 7
bit 6
bit 5
HDCLPLVL1 HDCLPLVL0 Reserved
bit 4
Reserved
bit 3
Reserved
bit 2
HDVUNMSK
default Value 0x04
bit 1
bit 0
HDVL1
HDVL0
SD Block Delay Register
Sub Address 0x13
bit 7
bit 6
SDCLPLVL1 SDCLPLVL0
bit 5
SYD2
bit 4
SYD1
bit 3
SYD0
bit 2
Reserved
default Value 0x00
bit 1
bit 0
Reserved
Reserved
The Limit level defined as this table.
HDCLPLVL[1:0]-bit
SDCLPLVL[1:0]-bit
Under-shoot Limit Level
00
no Clipping
01
Clipped at -7.0 IRE Level
10
Clipped at -1.5 IRE Level
11
Reserved
■ Black Burst Signal Generation Function
The AK8825can output Black Burst Signal (Black Level Output).
When HDBBG-bit of HD Mode Register (R/W) [Sub Address 0x00] in Component Video Encoder mode, SDBBG-bit of
SD Block Control Register (R/W) [Sub Address 0x11] is set to “1”, same operation is processed as in the case when the
fixed-16 Luminance signal and the fixed-Cb/Cr signal outputs are input. In this case when setup-bit is “ON”, set-up process is
done and when it is “OFF”, no set-up process is made.
HD Mode Register
Sub Address 0x00
bit 7
bit 6
HDCBG
HDBBG
bit 5
HDSETUP
bit 4
bit 3
HDEAVDEC HDCEA861
bit 2
HDMODE1
default Value 0x00
bit 1
bit 0
HDMODE0 HDRFRSH
SD Block Control Register
Sub Address 0x11
bit 7
bit 6
SDBBG
SDCBG
bit 5
SDSETUP
bit 4
SCR
bit 3
SDVM3
bit 2
SDVM2
Default Value 0x10
bit 1
bit 0
SDVM1
SDVM0
Rev-E-00
40
2008/03