AK8825 Datasheet, PDF (12/162 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

B1 PDN
C2 SDA
C1 SCL
D2 SELA
C9 HDO
B9 VDO
A5 DACO1
B6 DACO2
A6 DACO3
B3 VREF
A2 IREF
A3
A8
A4
B4
F1,H9
F2,G9,
J1,J6
D1
J5, F9
B2
BYPASS
FLT
AVDD
AVSS
DVDD
DVSS
PVDD1
PVDD2
BVSS
A1 TEST0
A9 TEST1
J9 TMO
A7, B5,
B7, B8,
C3, C8,
NC
E1, H8
Control Pin for Power Down and Reset.
AK8825 is initialized with PDN = Low.
P1
I AK8825 becomes Power down states during PDN=Low
Normal operation mode, PDN pin should be High.
This pin is Prohibited to be Hi-z States
P1
I/O
I2C Bus Data Input Pin.
Pulled up externally.
P1
I
I2C BUS clock input pin.
Pulled up externally.
P1
I
I2C BUS Address select pin.
Fixed to PVSS1 or PVDD1.
P2
O
Horizontal Sync Timing signal output pin.
In case of PDN pin = Low, this pin outputs Low.
P2
O
Vertical Sync Timing signal output pin.
In case of PDN Pin = Low, this pin outputs Low.
DAC1 output pin. Output signal is set by register
Composite Video Encoder mode:
Y or CVBS
A
O
Component Video Encoder mode:
Y or G
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
DAC2 output pin. Output signal is set by register
Composite Video Encoder mode:
Pb or B
A
O
Component Video Encoder mode:
C
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
DAC3 output pin. Output signal is set by register
Composite Video Encoder mode:
Pr or R
A
O
Component Video Encoder mode:
CVBS
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
A
I to be connected to AVDD via a 0.1 uF capacitor
A
O
Reference Current Output pin for DAC
Should be connected to AVSS via a 3.3 K ohm ( +/- 1 % ) resistor.
A
O
Output pin to output On-Chip VREF voltage.
Should be connected to AVSS via a larger-than 0.1 uF capacitor.
A
O Filter Pin for PLL
A
P Power supply pin for Analog.
A
G Ground pin for Analog
D
P Power supply pins for Digital.
D
G Ground pins for Digital.
P1
P Power supply pin for I/O(PDN, SDA, SCL, SELA)
P2
P Power supply pins for I/O(CLKIN, DATA[17:0], HDI, VDI)
A
G
Ground pin for Substrate.
Connect to AVSS.
TEST pin.
I
P1 Connect to DVSS.
(Internally Pull-down with approx. 100k-ohm)
TEST pin.
I
P2 Connect to DVSS.
(Internally Pull-down with approx. 100k-ohm)
TEST pin.
I/O P2 Leave open.
(Internally Pull-down with approx. 100k-ohm)
NCpins.
Leave open.
[AK8825]
Rev-E-00
12
2008/03