AK8825 Datasheet, PDF (143/162 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

SD Block Delay Register (R/W) [Sub Address 0x13]
[Composite Video Encoder Block]
to adjust YC Delay amount of output signal
Sub Address 0x13
bit 7
bit 6
SDCLPLVL1 SDCLPLVL0
0
0
bit 5
SYD2
0
bit 4
bit 3
SYD1
SYD0
Default Value
0
0
[AK8825]
bit 2
Reserved
0
default Value 0x00
bit 1
bit 0
Reserved
Reserved
0
0
BIT Register Name
bit 0
~
Reserved Reserved bit
bit 2
bit 3
SYD0
~
~
S-video Y Delay bit
bit 5
SYD2
bit 6 SDCLPLVL0
~
~
SD Clip Level Set bit
bit 7 SDCLPLVL1
R/W
Definition
R/W Reserved, write “0 “.
[[ SYD2 : SYD0 ] – bit
101: Y component output advances 3 clock times to C component.
110: Y component output advances 2 clock times to C component.
111: Y component output advances 1 clock time to C component.
000 : no delay between Y component and C component
R/W 001 : Y component output is delayed by 1 clock time to C
component.
010 : Y component output is delayed by 2 clock time to C
component.
011 : Y component output is delayed by 3 clock time to C
component.
to clip the under-shoot of the Over-Sampling Filter Outputs to a
pre-set value.
[ SDCLPLVL1:SDCLPLVL1 ]
R/W _{00: no clipping}
01: to be clipped at approximately - 7.0IRE
10: to be clipped at approximately -1.5IRE
11: reserved
Rev-E-00
143
2008/03