AK8825 Datasheet, PDF (14/162 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

28 DVSS
29 DATA16
30 PVDD2
31 DATA17
32 VDI
33 HDI
34 CLKIN
35 HDO
36 VDO
37 TEST1
38 FLT
39 DACO3
40 DACO2
41 DACO1
42 AVSS
43 AVDD
44 VREF
45 BYPASS
46 BVSS
47 IREF
48 TEST0
[AK8825]
D
G Ground pins for Digital.
Data Input pin
P2 I/O Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
P2
P Power supply pins for I/O(CLKIN, DATA[17:0], HDI, VDI)
Data Input pin
P2 I/O Refer “Data input Format”.
In case of PDN pin = Low, Hi-z states is possible.
In case of slave Synchronization operation mode, Vertical Sync timing should be
P2 I/O input.
In case of PDN pin = Low, Hi-z states is possible.
In case of slave Synchronization operation mode, Horizontal Sync timing should be
P2 I/O input.
In case of PDN pin = Low, Hi-z states is possible.
Clock Input Pin
Composite Video Encoder Mode: Input 27MHz Clock.
P2
I
Component Video Encoder Mode: Either 27MHz or 74.25MHz clock is input.
(Depending on Input Video Format)
High Speed Video DAC Mode: Max input clock is 54MHz.
Prohibited Hi-z States
P2
O
Horizontal Sync Timing signal output pin.
In case of PDN pin = Low, this pin outputs Low.
P2
O
Vertical Sync Timing signal output pin.
In case of PDN Pin = Low, this pin outputs Low.
TEST pin.
I
P2 Connect to DVSS.
(Internally Pull-down with approx. 100k-ohm)
A
O Filter Pin for PLL
DAC3 output pin. Output signal is set by register
Composite Video Encoder mode:
Pr or R
A
O
Component Video Encoder mode:
CVBS
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
DAC2 output pin. Output signal is set by register
Composite Video Encoder mode:
Pb or B
A
O
Component Video Encoder mode:
C
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
DAC1 output pin. Output signal is set by register
Composite Video Encoder mode:
Y or CVBS
A
O
Component Video Encoder mode:
Y or G
High Speed Video DAC mode:
Depending on Input data.
Load resistor is 300-ohm
A
G Ground pin for Analog
A
P Power supply pin for Analog.
A
I to be connected to AVDD via a 0.1 uF capacitor
A
O
Output pin to output On-Chip VREF voltage.
Should be connected to AVSS via a larger-than 0.1 uF capacitor.
A
G
Ground pin for Substrate.
Connect to AVSS.
A
O
Reference Current Output pin for DAC
Should be connected to AVSS via a 3.3 K ohm ( +/- 1 % ) resistor.
TEST pin.
I
P1 Connect to DVSS.
(Internally Pull-down with approx. 100k-ohm)
Power A: AVDD D: DVDD P1: PVDD1 P2: PVDD2
I/O: Input/Output pin I: Input pin O: Output pin G: Ground pin P: Power Supply pin
Pull Up / Down Pins
Rev-E-00
14
2008/03