AKD4632 Datasheet, PDF (4/48 Pages) Asahi Kasei Microsystems – AK4632 Evaluation board Rev.0

ASAHI KASEI
[AKD4632-A]
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
X’tal of 12.288MHz (Default) is set on the AKD4632-A. In this case, the AK4632 corresponds to PLL reference
clock of 12.288MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4632 is supplied to a
divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then “MCKO bit” in the
AK4632 is set to “1”. When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select
EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order
to much the output impedance of the clock generator.
JP6
MCKI
JP17
XTE
JP21
MCLK_SEL
JP18
MKFS
b) Set up jumper pins of BICK clock
JP20
BICK
XTL DIR EXT 256fs 512fs 1024fs MCKO
JP27
BICK
JP29
BICK_INV
JP19
BICK_SEL
INV THR DIR ADC INV THR 64fs _32fs 16fs _EXT
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4632 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
SDTI
JP26
4632_SDTI
DIR
ADC
DAC/LOOP ^ADC
<KM075602>
-4-
2005/04