AKD4632 Datasheet, PDF (3/48 Pages) Asahi Kasei Microsystems – AK4632 Evaluation board Rev.0

ASAHI KASEI
[AKD4632-A]
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X1. X’tal of 12.288MHz
(Default) is set on the AKD4632-A. Set “No.8 of SW3” to “H”.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA
connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
JP6
MCKI
JP17
XTE
JP21
MCLK_SEL
JP18
MKFS
XTL DIR EXT 256fs 512fs1024fs MCKO
b) Set up jumper pins of BICK clock
Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4632.
There is no necessity for set up JP19.
JP20
BICK
JP27
BICK
JP29
BICK_INV
JP19
BICK_SEL
INV THR DIR ADC INV THR 64fs _32fs 16fs _EXT
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4632 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
SDTI
JP26
4632_SDTI
DIR
ADC
DAC/LOOP ^ADC
<KM075602>
-3-
2005/04