AKD4632 Datasheet, PDF (2/48 Pages) Asahi Kasei Microsystems – AK4632 Evaluation board Rev.0

ASAHI KASEI
[AKD4632-A]
Evaluation Board Manual
„ Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, DVDD, SVDD, VVDD and VCC are supplied from the regulator. (AVDD, DVDD, SVDD,
VVDD and VCC jack should be open.). See “Other jumper pins set up (page 10)”. <default>
[REG]
[AVDD]
[DVDD]
[SVDD]
[VVDD]
[VCC]
[AVSS]
[AGND]
[DGND]
(red )
(orange)
(orange)
(blue)
(blue)
(orenge)
(black)
(black)
(black)
= 5V
= open
= open
= open
= open
= open
= 0V
= 0V
= 0V
: 3.3V is supplied to AVDD of AK4632 from regulator.
: 3.3V is supplied to DVDD of AK4632 from regulator.
: 3.3V is supplied to SVDD of AK4632 from regulator.
: 3.3V is supplied to VVDD of AK4632 from regulator.
: 3.3V is supplied to logic block from regulator.
: for analog ground
: for analog ground
: for logic ground
1-2) When AVDD, DVDD, SVDD, VVDD and VCC are not supplied from the regulator. (AVDD, DVDD,
SVDD, VVDD and VCC jack should be junction.) See “Other jumper pins set up (page 10)”.
[REG]
[AVDD]
[DVDD]
[SVDD]
[VVDD]
[VCC]
[AVSS]
[AGND]
[DGND]
(red)
(orange)
(orange)
(blue)
(blue)
(orenge)
(black)
(black)
(black)
= “REG” jack should be open.
= 2.6 ∼ 3.6V : for AVDD of AK4632 (typ. 3.3V)
= 2.6 ∼ 3.6V : for DVDD of AK4632 (typ. 3.3V)
= 2.6 ∼ 5.25V: for SVDD of AK4632 (typ. 3.3V, 5.0V)
= 2.6 ∼ 5.25V: for VVDD of AK4632 (typ. 3.3V, 5.0V)
= 2.6 ∼ 3.6V : for logic (typ. 3.3V)
= 0V
: for analog ground
= 0V
: for analog ground
= 0V
: for logic ground
Each supply line should be distributed from the power supply unit.
AVDD and DVDD must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4632 and AK4114 should be reset once bringing SW1, 2 “L” upon power-up.
„ Evaluation mode
In case of AK4632 evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4632 and AK4114. About AK4632’s audio interface format, refer to datasheet of AK4632. About
AK4114’s audio interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI
pin)
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or
FCK pin)
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
<KM075602>
-2-
2005/04