AK4122_1 Datasheet, PDF (4/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

ASAHI KASEI
[AK4122]
PIN/FUNCTION
No. Pin Name
1 CDTI
2 CDTO
3 TST1
4 INT2
5 TST2
6 TST3
7 M/S2
8 M/S3
9 SMUTE
10 TST4
11 TST5
12 FILT
13 AVSS
14 AVDD
15 TST6
16 RX1
17 TST7
18 RX2
19 TST8
20 RX3
21 TST9
22 RX4
23 TST10
24 TST11
I/O
Function
I Control Data Input Pin
O Control Data Output Pin
O Test 1 Pin
O Interrupt 2 Pin
O Test 2 Pin
Test 3 Pin
I
This pin should be connected to DVSS.
Master / Slave Mode Pin for PORT2
I
“H” : Master mode, “L” : Slave Mode
Master / Slave Mode Pin for PORT3
I
“H” : Master mode, “L” : Slave Mode
Soft Mute Pin
I
“H” : Soft Mute, “L” : Normal Operation
Test 4 Pin
I
This pin should be connected to AVSS.
Test 5 Pin
I
This pin should be connected to AVSS.
PLL Loop Filter Pin
O 470Ω±5% resistor and 2.2µF±50% ceramic capacitor in parallel with a
2.2nF±50% ceramic capacitor should be connected to AVSS externally.
- Analog Ground Pin
- Analog Power Supply Pin, 3.0 ∼ 3.6V
Test 6 Pin
I
This pin should be connected to AVSS.
I Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 7 Pin
I
This pin should be connected to AVSS.
I Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 8 Pin
I
This pin should be connected to AVSS.
I Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 9 Pin
I
This pin should be connected to AVSS.
I Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin)
Test 10 Pin
I
This pin should be connected to AVSS.
O Test 11 Pin
Note: All input pins except internal biased pins should not be left floating.
MS0267-E-03
-4-
2004/08