AK4122_1 Datasheet, PDF (36/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

ASAHI KASEI
[AK4122]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
Register Name
PDN & Mode Control
Selector & Clock Control
Audio Interface Format
DIR Control
INT0 Mask
INT1 Mask
DAT Mask & DTS Detect
Receiver Status 0
Receiver Status 1
Receiver Status 2
RX Channel Status Byte 0
RX Channel Status Byte 1
RX Channel Status Byte 2
RX Channel Status Byte 3
RX Channel Status Byte 4
Burst Preamble Pc Byte 0
Burst Preamble Pc Byte 1
Burst Preamble Pd Byte 0
Burst Preamble Pd Byte 1
Q-subcode Address / Control
Q-subcode Track
Q-subcode Index
Q-subcode Minute
Q-subcode Second
Q-subcode Frame
Q-subcode Zero
Q-subcode ABS Minute
Q-subcode ABS Second
Q-subcode ABS Frame
D7
XTL1
BYPS
0
CS12
MULK0
MULK1
0
UNLCK
DAT
0
CR7
CR15
CR23
CR31
CR39
PC7
PC15
PD7
PD15
Q9
Q17
Q25
Q33
Q41
Q49
Q57
Q65
Q73
Q81
D6
XTL0
OSEL
0
AMUTE
MPAR0
MPAR1
0
PAR
DTSCD
0
CR6
CR14
CR22
CR30
CR38
PC6
PC14
PD6
PD14
Q8
Q16
Q24
Q32
Q40
Q48
Q56
Q64
Q72
Q80
D5
TXE
ISEL1
0
EFH1
MAUT0
MAUT1
0
AUTO
NPCM
0
CR5
CR13
CR21
CR29
CR37
PC5
PC13
PD5
PD13
Q7
Q15
Q23
Q31
Q39
Q47
Q55
Q63
Q71
Q79
D4
SMUTE
ISEL0
ODIF
EFH0
MV0
MV1
0
V
PEM
0
CR4
CR12
CR20
CR28
CR36
PC4
PC12
PD4
PD12
Q6
Q14
Q22
Q30
Q38
Q46
Q54
Q62
Q70
Q78
D3
DEAU
ICKS1
IDIF1
IPS1
MAUD0
MAUD1
DTS16
AUDN
FS3
0
CR3
CR11
CR19
CR27
CR35
PC3
PC11
PD3
PD11
Q5
Q13
Q21
Q29
Q37
Q45
Q53
Q61
Q69
Q77
D2
DEM1
ICKS0
IDIF0
IPS0
MSTC0
MSTC1
DTS14
STC
FS2
0
CR2
CR10
CR18
CR26
CR34
PC2
PC10
PD2
PD10
Q4
Q12
Q20
Q28
Q36
Q44
Q52
Q60
Q68
Q76
D1
DEM0
OCKS1
DIF1
OPS1
MCIT0
MCIT1
MDAT1
CINT
FS1
CCRC
CR1
CR9
CR17
CR25
CR33
PC1
PC9
PD1
PD9
Q3
Q11
Q19
Q27
Q35
Q43
Q51
Q59
Q67
Q75
D0
PWN
OCKS0
DIF0
OPS0
MQIT0
MQIT1
MDAT0
QINT
FS0
QCRC
CR0
CR8
CR16
CR24
CR32
PC0
PC8
PD0
PD8
Q2
Q10
Q18
Q26
Q34
Q42
Q50
Q58
Q66
Q74
PDN pin = “L” resets the registers to their default values.
When PORT1 or PORT2 are selected as input port, the status registers (07H ∼ 1CH) are initialized.
Note. Unused bits must contain a “0” value.
Note. For addresses from 1DH ∼ 1FH, data must not be written.
MS0267-E-03
- 36 -
2004/08