AK4122_1 Datasheet, PDF (24/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

ASAHI KASEI
[AK4122]
„ System Reset
Bringing the PDN pin = “L” sets the AK4122 power-down mode and initializes the digital filter. When PDN pin = “L”,
the SDTO output is “L”. The AK4122 should be reset once by bringing PDN pin = “L” upon power-up. The SDTO is
valid from less than 100ms after the rising of PDN after clocks are supplied, and until then, outputs “L”. After the rising
of PDN pin, the SDTIO pin is input pin.
External clocks
(input / output port) ^{don’t care}
(stable)
don’t care
PDN
(internal state)
Power-down
< 100msec
PLL locktime & fs detection
normal operation
Power-down
SDTO
“0” data
Figure 13. System Reset
normal data
“0” data
„ Sequence of changing clocks
The recommended sequence of changing clocks is shown as Figure 14. The internal reset is executed when the input or
the output clocks are changed. The SDTO is placed “0” during reset. Within 100ms, the SDTO outputs normal data.
When the frequency transition occurs gradually without the phase change, the output data may have large distortion for
several seconds. Then, to output normal data within 100ms, a reset by PDN pin = “L” or PWN bit = “0” is recommended
when clocks are changed.
External clocks
(input port
state 1 (44.1kHz) (unknown)
or output port)
state 2 (48kHz)
PDN pin or
PWN bit
< 100msec
(internal state)
normal operation
Power down
PLL locktime
& fs detection
normal operation
SDTIO / SDTO normal data
Note1
normal data
SMUTE (Note2,
recommended)
0dB
Att.Level
-∞dB
1024/fso
1024/fso
Figure 14. Sequence of changing clocks
Note 1. The data on SDTO may cause click noise. If SDTI or SDTIO is “0” from GD before PDN pin goes “L”,
the data on SDTO keeps “0” then no unknown data is output.
Note 2. SMUTE can remove the unknown data.
MS0267-E-03
- 24 -
2004/08