AK4122_1 Datasheet, PDF (10/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
8.192
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High
LRCK for Input data (LRCK1, LRCK2)
Frequency
Duty Cycle
tCLKH 0.4/fCLK
fs
8
Duty
48
50
LRCK for Output data (LRCK, LRCK2)
Frequency
(Note 10)
fs
32
Duty Cycle
Slave Mode
Duty
48
50
Master Mode
Duty
50
S/PDIF Clock Recover Frequency
fPLL
32
Audio Interface Timing
Input for PORT1
BICK1 Period
tBCK
1/64fs
BICK1 Pulse Width Low
tBCKL
65
Pulse Width High
tBCKH
65
LRCK1 Edge to BICK1 “↑”
(Note 11) tLRB
30
BICK1 “↑” to LRCK1 Edge
(Note 11) tBLR
30
SDTI Hold Time from BICK1 “↑”
tSDH
30
SDTI Setup Time to BICK1 “↑”
tSDS
30
Input for PORT2 (Slave mode)
BICK2 Period
tBCK
1/64fs
BICK2 Pulse Width Low
tBCKL
65
Pulse Width High
tBCKH
65
LRCK2 Edge to BICK2 “↑”
(Note 11) tLRB
30
BICK2 “↑” to LRCK2 Edge
(Note 11) tBLR
30
SDTIO Hold Time from BICK2 “↑”
tSDH
30
SDTIO Setup Time to BICK2 “↑”
tSDS
30
Output for PORT2 (Slave mode)
BICK2 Period
tBCK
1/64fs
BICK2 Pulse Width Low
tBCKL
65
Pulse Width High
tBCKH
65
LRCK2 Edge to BICK2 “↑”
(Note 11) tLRB
30
BICK2 “↑” to LRCK2 Edge
(Note 11) tBLR
30
LRCK2 to SDTIO (MSB) (Except I²S mode) tLRS
BICK2 “↓” to SDTIO
tBSD
Note 10. Min value is 8kHz at BYPASS mode.
Note 11. BICK1 rising edge must not occur at the same time as LRCK1 edge.
BICK2 rising edge must not occur at the same time as LRCK2 edge.
[AK4122]
max
36.864
96
52
96
52
96
Units
MHz
ns
ns
kHz
%
kHz
%
%
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
ns
30
ns
MS0267-E-03
- 10 -
2004/08