AK4122_1 Datasheet, PDF (11/54 Pages) Asahi Kasei Microsystems – 24-Bit 96kHz SRC with DIR

ASAHI KASEI
Parameter
Symbol
min
typ
Output for PORT3 (Slave mode)
BICK Period
tBCK
1/64fs
BICK Pulse Width Low
tBCKL
65
Pulse Width High
tBCKH
65
LRCK Edge to BICK “↑”
(Note 11) tLRB
30
BICK “↑” to LRCK Edge
(Note 11) tBLR
30
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
BICK “↓” to SDTO
tBSD
Output for PORT2 (Master mode)
BICK2 Frequency
fBCK
64fs
BICK2 Duty
BICK2 “↓” to LRCK2
BICK2 “↓” to SDTIO
dBCK
50
tMBLR
−20
tBSD
−20
Output for PORT3 (Master mode)
BICK Frequency
fBCK
64fs
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
dBCK
50
tMBLR
−20
tBSD
−20
Control Interface Timing
CCLK Period
(Note 12) tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSW
150
tCSS
50
tCSH
50
CDTO Delay
CSN “↑” to CDTO Hi-Z
tDCD
tCCZ
Reset Timing
PDN Pulse Width
(Note 13)
tPD
150
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. In case of using INT2. When INT2 is not used, the max value is not limited.
Note 13. The AK4122 can be reset by bringing the PDN pin = “L”.
[AK4122]
max
30
30
20
30
20
30
1000
45
70
Units
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS0267-E-03
- 11 -
2004/08