CT2577 Datasheet, PDF (8/41 Pages) Aeroflex Circuit Technology – APPLICATION NOTE 108

Remote Terminal (RT) Mode
SEQUENCE OF OPERATION
The following section describes the sequence of operation for the various commands that
are received by the SmaRT unit in RT Mode.
RECEIVE COMMAND
An incoming command word is verified for all protocol checks (such as parity and bit count).
The verified command word is placed on the T0-15 bus and the NVCR signal is strobed. It is
at this time that a message can be illegalized.
Each successive data word after the command word is placed in an internal buffer FIFO.
This is done to double buffer the incoming data for complete message verification. Only
after the message is completely validated will the data be transferred to the internal RAM.
Otherwise, the contents of the FIFO is automatically flushed. This ensures that only valid
data will ever be read by the subsystem. The transfer from the FIFO to the RAM is
accomplished by a fast DMA burst. The guarantee of only valid data in RAM greatly
simplifies a MIL-STD-1553 RT implementation. Error handling of data is not required by the
subsystem.
The subsystem is allowed the most flexibility to access the RAM without contending with
1553 bus traffic. In 1553, data words are received at a rate of 20 µSec per word or a
maximum time of 640 µSec for a 32 word transfer. Many other systems do not buffer the
incoming data at all. That means that the RAM is periodically being updated with data words
into the RAM for up to 640 µSeconds. If an error occurs, the corrupt data is already in
memory and must be sorted out by the subsystem microprocessor. The Smart unit buffers
the data so that the RAM is completely available to the subsystem until the DMA transfer to
RAM occurs. The possibilities of memory contention is greatly reduced and the contents of
RAM is guaranteed to be valid.
When the entire set of received data words are transferred to the buffer FIFO, the
NCMDSTRB goes low indicating that a completely validated message has been received.
The received Command Word again appears on the T0-15 bus at this time. The end of the
NCMDSTRB strobe will initiate the DMA cycle to transfer the data words from the buffer
FIFO to internal RAM. The NCMDSTRB pulse is 8.5 µSec long and during this time interval,
the bus arbitration logic is active. If the subsystem has already begun a read/write operation
before NCMDSTRB, the NACK (acknowledge) signal will go low for 500 nSec allowing the
completion of the read/write command. The read/write operation must be completed within
the remaining 8 µSec. If a read/write operation starts after the NCMDSTRB strobe has
begun, the NACK will not occur and thus hold off the subsystem for the duration of the DMA
cycle to internal RAM.
During NCMDSTRB, the Command Word is loaded into the Command/Status FIFO stack
and the NEMPTY line goes high. The user can utilize this signal as an indication that some
activity has occurred. The Command/Status FIFO stores up to 32 command words for the
subsystem to review. This allows the processor to only response to the 1553 unit when
something has occurred. Constant polling of the 1553 unit is not required. To reduce
APPLICATION NOTE #108
8
Released 9/98