CT2577 Datasheet, PDF (11/41 Pages) Aeroflex Circuit Technology – APPLICATION NOTE 108

/ writes and store them in the buffer instead. The user accesses the same locations as if they
would if they were directly accessing the main RAM.
The block transfer logic is enabled with signal NENBTL (pin A7) being active low and is not
applicable to subaddress 00 and 1F (unless McAir is selected) areas of ram. The block
transfer logic may also be configured by writing to certain address locations providing
NENBTL is selected, ie.
0 1 00 02
0 1 00 03
0 1 00 04
0 1 00 05
402h
403h
404h
405h
Disable Read
Disable Read
Enable Read
Enable Read
Disable Write
Enable Write
Disable Write
Enable Write
Reset will enable both Write and Read.
Note: All 257X versions with internal RAM that do not have NENBTL as a dsiscrete input
have it enabled internally.
READ (RECEIVE)
The Read BTL functions similarly to the Write BTL in that the BTL buffers the read activity. A
subsystem read will initially generate a DMA of that entire portion of the subaddress to be
stored in the BTL buffer. The subsystem can then read out the data at its leisure while the
main RAM is free for future updates. Since the entire portion of the subaddress data was
DMA from the RAM, the data read from the BTL buffer is guaranteed contiguous.
The user must read data from the device in a specific sequence starting with the first word
received in the n-1 location and ending with the last word received in location 00 of the
subaddress. The BTL will sense the read from location 00 and reset the sequence ready for
a new access.
1. The first word of a received message will be read first, this will initiate a burst DMA
transfer of a complete message from main memory to the 32 word BTL buffer memory,
during which time the subsystem will be locked out. Data is transferred at the rate of 250
ns per word.
2. The sub system can then read data from the ram at its leisure. The last word to be read
will be the last word received in the message and read from location zero. This will reset
the block transfer logic.
3. If the 1553 DMA transfer to the main RAM becomes active during the burst transfer, the
transfer will complete and then be locked out until the 1553 is complete. However the 32
word BTL buffer memory will be accessible to the subsystem at this time to read out the
data.
4. If the 1553 DMA transfer to the main RAM becomes active before the start of the burst
transfer, the transfer will belocked out until the 1553 is complete. The sub system will be
locked out during this time (main ram being accessed by the 1553 and the 32 word buffer
memory is waiting for the receive message). When the 1553 is complete the burst
transfer will take place and then unlock the subsystem.
APPLICATION NOTE #108
11
Released 9/98