CT2577 Datasheet, PDF (15/41 Pages) Aeroflex Circuit Technology – APPLICATION NOTE 108

by the 1553 and the BTL buffer memory is full). If the BTL memory is not fully loaded, the
subsystem can continue to load the BTL memory until full (write to 00 indicates a full
condition). When the 1553 is complete the burst transfer will take place and then unlock
the subsystem.
7. Once the burst transfer has commenced it will complete, thus ensuring data consistency.
The DMA cycle begins after the rising edge of NCMDSTRB. All requested data words are
placed in an internal buffer FIFO. This is done to double buffer the outgoing data as a
contiguous block and free up the internal RAM as quickly as possible. The DMA cycle
transfers words from internal RAM at a rate of one word each 1 µSec. The maximum DMA
cycle time would occur for a 32 data word transfer or 32 µSec. Maximum subsystem hold-off
time would be 8.5µSec + 32 µSec for a total of 40.5 µSec.
CHANGING THE STATUS WORD BITS
There are four Status word bits that can be altered by the subsystem through simple write
operations. These four bits and addresses are as follows:
SERVREQ
0 0 00 08
008h
BUSY
0 0 00 04
004h
SSFLAG
0 0 00 02
002h
DBCA
0 0 00 01
001h
See Memory Map for further details.
DEVICE STATUS
The status of the device may be determined by reading from location 0 00 01, the status bits
and BTL status will be available on DATA pins 0-7.
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DBCA
SSFLAG
SSBUSY
SERVREQ
BTL WRITE ENABLED
BTL READ ENABLED
OFF-LINE SELF TEST ENABLED
ON-LINE SELF TEST ENABLED
See Memory Map for further details.
BIT REGISTER
With MCAIR (pin F1) disabled, writing data to 0 1 00 13 or 0 1 1F 13 will set the content of
the BIT register. The data may also be read from these locations. This register is
non-resetable. See Memory Map for further details.
APPLICATION NOTE #108
15
Released 9/98