CT2577 Datasheet, PDF (4/41 Pages) Aeroflex Circuit Technology – APPLICATION NOTE 108

NVALCHK
STATUS
NHDR
STREL
LA
incoming data for correct checksum and generate the correct checksum word for an
outgoing data transfer.
"0" input to this pin ENABLES the checksum circuitry.
"1" input to this pin Disables the checksum circuitry.
Latched version of the STATUS signal. NVALCHK is latched on the falling edge of
NCMDSTRB (RT) or NSTSTRB (BC) and will remain stable until the next
NCMDSTRB or NSTSTRB.
"0" output to this pin means the checksum was VALID.
"1" output to this pin means the checksum was NOT VALID.
Open drain output will toggle high or low on each incoming data word from the 1553
databus provided NENCHK is enabled. When the last data word is received the
STATUS line is sampled by the protocol circuitry to determine if the checksum for the
message is valid. At the end of the message, if STATUS is low then the checksum is
not valid. This STATUS signal can be wired to several different pins to customise the
units response to achecksum failure. STATUS can be wired to signals such as
NILLCMD and NSR which would cause the message to be illegalised and set Service
Request bit in the Status.
In MIL-STD-1760, the first data word of a message is defined as a Header word. The
NHDR signal indicates the presence of the Header word on the T0-T15 highway as it
is received. The user can also read the Header word from RAM.
"0" on this pin means the Header Word is on the T0-15 Bus
When the store is released from the aircraft all the Remote Terminal address inputs
go high causing signal STREL to go high
Enables the Latched Address Option. Normally, the RT address lines are constantly
monitored and compared to the incoming Command Word. When enabled, the RT
address lines levels are internally latched every time the unit is reset. The latched RT
address information is then compared to the incoming Command Word. This latched
address function complies with the requirements of MIL-STD-1760.
"0" on this pin means the RT address lines are NOT latched
"1" on this pin means the RT address lines are latched
Bus Interface Signals
ADIN0-11
12 bit address input to the unit specifying what location the user will be access-
ing in the RAM / registers. These address inputs are inverted when the Multibus inter-
face is selected.
BCNRT
Indicates what mode the unit is in.
"0" = RT Mode
"1" = BC Mode
NCARDEN
Used as a Device Select. Signal to indicate the processor is addressing this unit. The
user can use this signal tied to an address decoder to enable the unit for a read/write
operation.
"0" = Enable unit for I/O operations
"1" = DISABLE unit for I/O operations
C16Mhz 16 Mhz clock system clock.
APPLICATION NOTE #108
4
Released 9/98