CT2577 Datasheet, PDF (12/41 Pages) Aeroflex Circuit Technology – APPLICATION NOTE 108

5. Once the burst transfer has commenced it will complete, thus ensuring data consistency.
DMA TRANSFER TIMES
The DMA cycle transfers words from the FIFO to internal RAM at a rate of one word each 1
µSec. The maximum DMA cycle time could possibly occur for a 32 data word transfer if the
RAM is accessed at the beginning of NCMDSTRB Strobe. Maximum subsystem hold-off
time would be 8.5 µSec (NCMDSTRB Signal) + 32 µSec (0.5 µSec per word) for a total of
24.5 µSec.
TRANSMIT COMMAND
The incoming command word is verified for all protocol checks (such as parity and bit count).
The verified command word is placed on the T0-15 bus and the NVCR signal is strobed. It is
at this time that a message can be illegalized.
T0-15
NVCR
CMD WD
NME
500 nSec
600 nSec
Max
Any message can be illegalized by applying an active low on the NME signal within 600
nSec of the rising edge of NVCR at this time. The RT will respond with a Status word having
the Message Error bit set. See Section 1.2.1.1 for implementing the Message Illegalization.
The NCMDSTRB goes low indicating that a completely validated message has been
received. The validated Command Word again appears on the T0-15 bus at this time. The
end of the NCMDSTRB strobe will initiate the DMA cycle to transfer the data words from
internal RAM to the buffer FIFO.
Buffering the outgoing message with a FIFO means that the subsystem is allowed the most
flexibility to access the RAM without contending with 1553 bus traffic. In 1553, data words
are transmitted at a rate of 20 µSec per word or a maximum time of 640 µSec for a 32 word
transfer. Many other systems do not buffer the outgoing data at all. That means that the
RAM is periodically being accessed for data words from the RAM for up to 640 µSeconds.
The SmaRT unit buffers the outgoing data so that the RAM is completely available to the
subsystem after the DMA transfer from RAM occurs. The possibilities of memory contention
is greatly reduced and the contents of the outgoing data will not be affected by subsystem
operations.
The NCMDSTRB pulse is 8.5 µSec long and during this time interval, the bus arbitration
logic is active. If the subsystem has already begun a read/write operation before
NCMDSTRB, the NACK (acknowledge) signal will go low for 500 nSec allowing the
APPLICATION NOTE #108
12
Released 9/98