ADP5586 Datasheet, PDF (9/44 Pages) Analog Devices – Keypad Decoder and I/O Port Expander

Data Sheet
FUNCTIONAL DESCRIPTION
EVENT FIFO
Before going into detail on the various blocks of the ADP5586,
it is important to understand the function of the event FIFO that
is featured in the ADP5586. The event FIFO (Register 0x03 to
Register 0x12) can record as many as 16 events. By default, the
FIFO primarily records key events, such as key press and key
release. However, it is possible to configure the general-purpose
input (GPI) and logic activity to generate event information
on the FIFO, as well. An event count, EC[4:0] (Register 0x02,
Bits[4:0]), is composed of five bits and works in tandem with
the FIFO so that the user knows how many events are stored
in the FIFO.
The FIFO consists of sixteen 8-bit elements. Bits[6:0] of each
element store the event identifier, and Bit 7 stores the event
state. The user can read the top element of the FIFO from any
of the FIFO_1 through FIFO_16 registers. The ADP5586 has
multiple copies of the FIFO register to allow reading of the
complete FIFO with a single I²C burst read.
OVRFLOW_INT
KEY EVENTS
GPI EVENTS
LOGIC EVENTS
FIFO
UPDATE
EC[4:0]
EVENT1[7:0]
EVENT2[7:0]
EVENT3[7:0]
EVENT4[7:0]
EVENT5[7:0]
EVENT6[7:0]
EVENT7[7:0]
EVENT8[7:0]
EVENT9[7:0]
EVENT10[7:0]
EVENT11[7:0]
EVENT12[7:0]
EVENT13[7:0]
EVENT14[7:0]
EVENT15[7:0]
EVENT16[7:0]
76543210
EVENT8_IDENTIFIER[6:0]
EVENT8_STATE
Figure 6. Breakdown of Eventx[7:0] Bits
ADP5586
FIRST
READ
EC = 3
KEY 3 PRESSED
KEY 3 RELEASED
GPI 7 ACTIVE
SECOND
READ
EC = 2
KEY 3 RELEASED
GPI 7 ACTIVE
THIRD
READ
EC = 1
GPI 7 ACTIVE
EC = 0
Figure 7. FIFO Operation
The FIFO registers always point to the top of the FIFO (that is, the
location of EVENT1[7:0]). If the user tries to read back from any
location in a FIFO, data is always obtained from the top of that
FIFO. This ensures that events can be read back only in the order
in which they occurred, thereby ensuring the integrity of the
FIFO system.
As stated previously, some of the on-board functions of the
ADP5586 can be programmed to generate events on the FIFO.
A FIFO update control block manages updates to the FIFO.
If an I²C transaction is accessing any of the FIFO address
locations, updates are paused until the I²C transaction is complete.
A FIFO overflow event occurs when more than 16 events are
generated prior to an external processor reading a FIFO and
clearing it.
If an overflow condition occurs, the overflow interrupt status
bit is set (OVRFLOW_INT, Register 0x01, Bit 2). An interrupt
is generated if an overflow interrupt is enabled, signaling to the
processor that more than 16 events have occurred.
Rev. 0 | Page 9 of 44