ADP5586 Datasheet, PDF (37/44 Pages) Analog Devices – Keypad Decoder and I/O Port Expander

Data Sheet
ADP5586
PULSE_GEN_CONFIG, Register 0x35
Table 62. PULSE_GEN_CONFIG Bit Descriptions
Bits Bit Name
Access
Description
7 PULSE_GEN_1_INV
Read/write
0 = no inversion on Pulse Generator 1. On time is defined as the length of time a high
signal is output.
1 = inverted output on Pulse Generator 1. On time is defined as the length of time a high
signal is output.
6 PULSE_GEN_1_ON_CLK Read/write Defines clock speed for the on time of Pulse Generator 1.
0 = 1 ms.
1 = 125 ms.
Setting PULSE_GEN_1_ON_CLK = 1 and PULSE_GEN_1_PRD_CLK = 0 is not a supported
configuration.
5 PULSE_GEN_1_PRD_CLK Read/write Defines clock speed for the period of Pulse Generator 1.
0 = 1 ms.
1 = 125 ms.
Setting PULSE_GEN_1_ON_CLK = 1 and PULSE_GEN_1_PRD_CLK = 0 is not a supported
configuration.
4 PULSE_GEN_1_EN
Read/write 0 = Pulse Generator 1 is disabled. The off signal is output constantly.
1= Pulse Generator 1 is enabled.
3 PULSE_GEN_2_INV
Read/write
0 = no inversion on Pulse Generator 2. On time is defined as the length of time a high
signal is output.
1 = inverted output on Pulse Generator 2. On time is defined as the length of time a low
signal is output.
2 PULSE_GEN_2_ON_CLK Read/write Defines clock speed for the on time of Pulse Generator 2.
0 = 1 ms.
1 = 125 ms.
Setting PULSE_GEN_2_ON_CLK = 1 and PULSE_GEN_2_PRD_CLK = 0 is not a supported
configuration.
1 PULSE_GEN_2_PRD_CLK Read/write Defines clock speed for the period of Pulse Generator 2.
0 = 1 ms.
1 = 125 ms.
Setting PULSE_GEN_2_ON_CLK = 1 and PULSE_GEN_2_PRD_CLK = 0 is not a supported
configuration.
0 PULSE_GEN_2_EN
Read/write 0 = Pulse Generator 2 is disabled. The off signal is output constantly.
1 = Pulse Generator 2 is enabled.
LOGIC_CFG, Register 0x36
Table 63. LOGIC_CFG Bit Descriptions
Bits Bit Name
Access
7 Reserved
Reserved
6 LY_INV
Read/write
5 LC_INV
Read/write
4 LB_INV
Read/write
3 LA_INV
Read/write
[2:0] LOGIC_SEL[2:0]
Read/write
Description
Reserved.
0 = the LY output is not inverted before passing into the logic block.
1 = inverts the LY output from the logic block.
0 = the LC input is not inverted before passing into the logic block.
1 = inverts LC input before passing it into the logic block.
0 = the LB input is not inverted before passing into the logic block.
1 = inverts LB input before passing it into the logic block.
0 = the LA input is not inverted before passing into the logic block.
1 = inverts LA input before passing it into the logic block.
Configures the digital mux for the logic block. Refer to Figure 19.
000 = off/disable.
001 = AND.
010 = OR.
011 = XOR.
100 = FF.
101 = IN_LA.
110 = IN_LB.
111 = IN_LC.
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