ADP5586 Datasheet, PDF (14/44 Pages) Analog Devices – Keypad Decoder and I/O Port Expander

ADP5586
Data Sheet
LOGIC BLOCK
Several of the ADP5586 input/output lines can be used as inputs
and outputs for implementing some common logic functions.
The R1, R2, and R3 input/output pins can be used as inputs,
and the R0 input/output pin can be used as an output for the
logic block. When the R1, R2, and R3 input lines are used, the
GPIO_4_INP_EN, GPIO_3_INP_EN, and GPIO_2_INP_EN
bits (Register 0x29, Bits[3:1]) must be enabled to accept inputs.
When the R0 pin is used as an output for the logic block, the
GPIO_1_OUT_EN bit (Register 0x27, Bit 0) must be enabled.
The outputs from the logic block can be configured to generate
interrupts. They can also be configured to generate events on
the FIFO.
Figure 19 shows a detailed diagram of the internal makeup of
the logic block, illustrating the possible logic functions that can
be implemented.
LOGIC BLOCK
(R1) LA
(R2) LB
(R3) LC
LA_INV
LB_INV
LC_INV
LY_INV
FF_SET
FF_CLR
LOGIC_SEL[2:0]
R3_EXTEND_CFG
SET
DQ
CLR
LY (R0)
LOGIC_INT_LEVEL
LOGIC_EVENT_EN
RESET_TRIG_TIME[3:0]
RESET_EVENT_A[7:0]
RESET_EVENT_B[7:0]
RESET_EVENT_C[7:0]
I²C BUSY
KEY EVENT
GPI EVENT
LOGIC
LOGIC EVENT
EVENT/INT
GENERATOR
FIFO
UPDATE
OVRFLOW_INT
EC[4:0]
FIFO
EVENT_INT
LOGIC_INT
Figure 18. Logic Block Overview
LA
LA
LA ^{0 OUT IN_LA}
1
SEL
LA_INV
IN_LA
IN_LB
AND
0
AND
OUT
IN_LC
AND ¹
SEL
MUX
LB
0
IN_LB
GND
LB
LB
OUT
000
1
SEL
LB_INV
IN_LA _OR
IN_LB
IN_LC
0 _OUT OR
OR ¹
SEL
AND
001
OR
010
XOR
LY
011
0
LY
LC
LC
0
IN_LC
LC
OUT
IN_LA _XOR
1
IN_LB
0
XOR
OUT
FF
IN_LA
OUT
100
101
LY
OUT
1
SEL
SEL
XOR ¹
IN_LB
LY_INV
IN_LC
SEL
110
LC_INV
IN_LC
111
FF_SET
SEL[2:0]
IN_LA
SET
D Q _FF
LOGIC_SEL[2:0]
IN_LB
FF_CLR
IN_LC
0
OUT
1
SEL
CLR
R3_EXTEND_CFG = 1
Figure 19. Logic Block Internal Makeup
Rev. 0 | Page 14 of 44