ADP5586 Datasheet, PDF (4/44 Pages) Analog Devices – Keypad Decoder and I/O Port Expander

ADP5586
Data Sheet
I²C TIMING SPECIFICATIONS
Table 2.
Parameter
I²C TIMING SPECIFICATIONS
Delay from UVLO/RST Inactive to I²C Access
fSCL
tHIGH
tLOW
tSU; DAT
tHD; DAT
tSU; STA
tHD; STA
tBUF
tSU; STO
tVD; DAT
tVD; ACK
tR
tF
tSP
CB¹
Description
SCL clock frequency
SCL high time
SCL low time
Data setup time
Data hold time
Setup time for repeated start
Hold time for start/repeated start
Bus free time for stop and start conditions
Setup time for stop condition
Data valid time
Data valid acknowledge
Rise time for SCL and SDA
Fall time for SCL and SDA
Pulse width of suppressed spike
Capacitive load for each bus line
1 _{CB is the total capacitance of one bus line in picofarads (pF).}
Timing Diagram
t_F
t_R
t_{SU; DAT}
70%
SDA _30%
70%
30%
t_F
t_{HD; DAT}
SCL
S
70%
30%
70%
30%
t_{HD; STA}
1/f_SCL
FIRST CLOCK CYCLE
SDA
t_{SU; STA}
t_{HD; STA tSP}
t_R
70%
30%
t_LOW
t_HIGH
t_{VD; DAT}
70%
30%
t_BUF
t_{VD; ACK tSU; STO}
SCL
Sr
V_IL = 0.3V × VDD
V_IH = 0.7V × VDD
70%
30%
P
S
NINTH CLOCK
Figure 2. I²C Interface Timing Diagram
Min
Max
60
0
1000
0.26
0.5
50
0
0.26
0.26
0.5
0.26
0.45
0.45
120
120
0
50
550
NINTH CLOCK
Unit
μs
kHz
μs
μs
ns
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
pF
Rev. 0 | Page 4 of 44