ADP5586 Datasheet, PDF (16/44 Pages) Analog Devices – Keypad Decoder and I/O Port Expander

ADP5586
Data Sheet
PULSE GENERATORS
The ADP5586 contains two pulse generators that are suitable for
driving indicator LED drive signals, as well as watchdog timers
and other extended time pulsed applications. The ADP5586 allows
for eight bits of definition for both the on time and period of the
generated pulse. To allow for extended timings, the user can choose
between a 1 ms clock and a 125 ms clock to increment these timers.
The PULSE_GEN_1_PERIOD and PULSE_GEN_2_PERIOD
registers (Register 0x30 and Register 0x33, respectively) define
the periods of the two pulse generators. Choosing a clock period
of 125 ms in the PULSE_GEN_CONFIG register (Register 0x35,
Bit 1 and Bit 5) allows for the setting of pulse generator periods
of up to 31.875 sec. Setting the PULSE_GEN_x_ON_CLK bit to
a step size of 125 ms and the PULSE_GEN_x_PRD_CLK bit to
a step size of 1 ms is not a supported configuration.
To support active low applications, a signal inversion can be
programmed in the PULSE_GEN_CONFIG register, using Bit 7
and Bit 3 (PULSE_GEN_x_INV). Delays can be introduced to
create synchronized offsets between the channels. If both channels
are enabled at the same time (that is, enabled from the same I²C
write), the difference in delays is the offset between the channels.
If a single channel is active and delays are to be synchronized,
the user must first disable both pulse generators before enabling
both pulse generators with the same I²C write command. The
delay counter uses the same clock selection as the period counter.
See Table 56 through Table 61 for more details. To enable pulse
generator output on C1 and/or C0, the GPIO_8_OUT_EN bit
and/or the GPIO_7_OUT_EN bit (Register 0x28, Bits[1:0])
must be enabled.
PULSE_GEN_x_ON_CLK
1ms CLOCK
0
125ms CLOCK
1
ON TIME COUNTER x
PULSE_GEN_x_ON_TIME[7:0]
0
1
PULSE_GEN_x_PRD_CLK
PERIOD COUNTER x
PULSE_GEN_x_PERIOD[7:0]
DELAY COUNTER x
PULSE_GEN_x_EN
PULSE
GENERATOR
PULSE_GEN_x
PULSE_GEN_x_INV
PULSE_GEN_x_DELAY[7:0]
Figure 22. Pulse Generator Block Diagram
DELAY 1
SDA/SCL
PULSE_GEN_1
ON TIME 1
PULSE_GEN_2
PERIOD 1
ON TIME 2
DELAY 2
PERIOD 2
Figure 23. Example Pulse Generator Timing
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