AD9558 Datasheet, PDF (89/104 Pages) Analog Devices – Quad Input Multiservice Line Card Adaptive

Data Sheet
AD9558
REFB Profile (Register 0x0740 to Register 0x0766)
REFB Profile Register 0x0740 to Register 0x0766 are identical to REFA Profile Register 0x0700 to Register 0x0726.
REFC Profile (Register 0x0780 to Register 0x07A6)
REFC Profile Register 0x0780 to Register 0x07A6 are identical to REFA Profile Register 0x0700 Register 0x0726.
REFD Profile (Register 0x07C0 to Register 0x07E6)
REFD Profile Register 0x07C0 to Register 0x07E6 are identical to REFA Profile Register 0x0700 to Register 0x0726.
OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10)
Table 89. General Power-Down
Address Bits Bit Name
0x0A00 7 Soft reset exclude regmap
6 DCO power-down
5 SYSCLK power-down
5 Reference input power-down
3 TDC power-down
2 APLL power-down
1 Clock dist power-down
0 Full power-down
Description
Resets device but retains programmed register values (default: not reset)
Places DCO in deep sleep mode (default: not powered down)
Places SYSCLK input and PLL in deep sleep mode (default: not powered down)
Places reference clock inputs in deep sleep mode (default: not powered down)
Places the time-to-digital converter in deep sleep mode (default: not powered down)
Places the output PLL in deep sleep mode (default: not powered down)
Places the clock distribution outputs in deep sleep mode (default: not powered down)
Places the entire device in deep sleep mode (default: not powered down)
Table 90. Loop Mode
Address Bits Bit Name
0x0A01 7 Reserved
6 User holdover
5 User freerun
[4:2] REF switchover mode
[1:0] User reference in manual
switchover mode
Description
Reserved.
Forces the device into holdover mode (default: not forced holdover mode).
If a tuning word history is available, then the history tuning word specifies the DCO
output frequency. Otherwise, the free run frequency tuning word register specifies the
DCO output frequency.
The phase and frequency lock detectors are forced into the unlocked state.
Forces the device into user free run mode (default is not forced user free run mode).
The free run frequency tuning word register specifies the DCO output frequency. When
the user freerun bit is set, it overrides the user holdover bit (Address 0x0A01, Bit 6).
Selects the operating mode of the reference switching state machine.
Reference Switchover Mode, Bits[2:0]
Register 0x0A01[4:2]
Reference Selection Mode
000 (default)
001
010
011
100
101
110
111
Automatic revertive mode
Automatic nonrevertive mode
Manual reference select
(with automatic fallback mode)
Manual reference select mode
(with auto-holdover)
Full manual mode (no auto-holdover)
Not used
Not used
Not used
Input reference when REF switchover mode bits (Register 0x0A01, Bits[4:2]) = 010, 011, or 100.
00 (default) = Input Reference A.
01 = Input Reference B.
10 = Input Reference C.
11 = Input Reference D.
Table 91. Cal/Sync Distribution
Address Bits Bit Name
0x0A02 [7:2] Reserved
1 Soft sync clock distribution
0 Reserved
Description
Default: 0x00
Setting this bit initiates synchronization of the clock distribution output (default: 0b).
Nonmasked outputs stall when value is 1b; restart is initialized on 1b to 0b transition.
Default: 0b.
Rev. A | Page 89 of 104