AD9558 Datasheet, PDF (60/104 Pages) Analog Devices – Quad Input Multiservice Line Card Adaptive

AD9558
Data Sheet
Table 33. Preset Output Frequencies for Hard Pin and Soft Pin Programming
Freq ID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Frequency (MHz)
19.44
25
125
156.7071
622.08
625
644.53125
657.421875
660.184152
666.5143
669.3266
672.1627
690.5692
693.4830
698.8124
704.380580
Frequency Description
19.44 MHz
25 MHz
125 MHz
156.25 MHz × 1027/1024
622.08 MHz
625 MHz
625 MHz × 33/32
657.421875 MHz
657.421875 MHz × 239/238
622.08 MHz × 255/238
622.08 MHz × 255/237
622.08 MHz × 255/236
644.53125 MHz × 255/238
644.53125 MHz × 255/237
622.08 MHz × 255/237
657.421875 MHz × 255/238
Hard Pin Program
PINCONTROL = High
M3
M2
M1
0
0
0
0
0
½
0
0
1
0
½
0
0
½
½
0
½
1
0
1
0
0
1
½
0
1
1
½
0
0
½
0
½
½
0
1
½
½
0
½
½
½
½
½
1
½
1
0
Soft Pin Program
PINCONTROL = Low,
Register 0x0C01[3:0]
B7
B6
B5
B4
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Table 34. System Clock Configuration in Hard Pin and Soft Pin Programming Modes
Freq ID
0
1
2
3
Frequency (MHz)
49.152
49.152
24.576
98.304
System Clock Configuration
XTAL mode, doubler on, N = 8
XTAL mode off, doubler on, N = 8
XTAL mode, doubler on, N = 16
XTAL mode off, doubler off, N = 8
Hard Pin Program
PINCONTROL = High,
IRQ Pin
IRQ Pin
0
½
1
N/A
Soft Pin Program
PINCONTROL = Low,
Register 0x0C02[1:0]
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Equivalent
System Clock
PLL Register
Settings
0001, 0000, 1000
HARD PIN PROGRAMMING MODE
The state of the PINCONTROL pin at power-up controls whether
or not the chip is in hard pin programming mode. Setting the
PINCONTROL pin high disables the I²C protocol, although the
register map can be accessed via the SPI protocol.
The M0, M5, and M4 pins select one of 16 input frequencies, and
the M3 to M1 pins select one of 16 possible output frequencies. See
Table 32 and Table 33 for details.
The system clock configuration is controlled by the state of the
IRQ pin at startup (see Table 34 for details). The digital PLL
loop bandwidth, reference input frequency accuracy tolerance
ranges, and DPLL phase margin selection are not available in
hard pin programming mode unless the user uses the serial port
to change their default values.
When in hard pin programming mode, the user must set
Register 0x0200[0] = 1 to activate the IRQ, REF status, and PLL
lock status signals at the multifunction pins.
Rev. A | Page 60 of 104