AD9558 Datasheet, PDF (86/104 Pages) Analog Devices – Quad Input Multiservice Line Card Adaptive

AD9558
Data Sheet
FRAME SYNCHRONIZATION (REGISTER 0x0640 TO REGISTER 0x0641)
Table 77. Frame Sync Setting
Address
Bit(s)
Bit Name
0x0640
[7:1]
Reserved
0
Enable Fsync
0x0641
[7:4]
3
Reserved
Validate Fsync ref
2
Fsync one shot
1
Fsync arm method
0
Arm soft Fsync
Description
Reserved; default: 0x00.
Enable frame synchronization.
0 (default) = frame synchronization disabled.
1 = frame synchronization enabled.
Reserved; default: 0x00.
Setting this bit forces the reference validation logic to declare REFA valid only if the
REFB (the sync pulse) input is also valid. This bit can be thought as a logical AND of
REFA VALID and REFB VALID signals . If REFC is selected, this bit requires that REFD
(the sync pulse) input also be valid before declaring REFC valid.
0 (default) = only the selected reference input must be valid.
1 = the sync pulse input must also be valid to validate the selected input.
Selects one-shot or level-sensitve frame sync function.
0 (default) = use level-sensitive frame sync. Frame sync occurs on every edge of the
frame pulse.
1 = use one-shot frame sync. Frame sync occurs only on the first frame sync pulse
(on REFB or REFD). User must re-arm by raising the SYNC pin high and then low, or
by clearing and resetting the arm soft Fsync bit. As with all buffered regsiters, an
I/O update is required (Register 0x0005[0] = 0x01) after writing this register.
Selects which signal is used to arm the frame sync
0 (default) = use SYNC pin.
1 = use arm soft Fsync (Register 0x0641[0]).
Arms frame sync after I/O update. Next pulse on REFB or REFD is the sync pulse. The
Fsync arm method bit must also be set for this bit to take effect.
0 = (default); frame sync unarmed.
1 = frame sync armed.
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