AD9558 Datasheet, PDF (29/104 Pages) Analog Devices – Quad Input Multiservice Line Card Adaptive

Data Sheet
AD9558
THEORY OF OPERATION
SYNC
RESET PINCONTROL M0 M1 M2 M3 M4 M5 M6 M7 IRQ
XO OR XTAL _{XO FREQUENCIES}
10MHz TO 180MHz
XTAL: 10MHz TO 50MHz
÷M0 TO ÷M3b ARE
10-BIT INTEGER
DIVIDERS
SPI/I²C
REFA
REFA
REFB
REFB
REFC
REFC
REFD
REFD
SPI/I²C
SERIAL PORT
EEPROM
REGISTER
SPACE
÷2
ROM
AND
FSM
MULTIFUNCTION I/O PINS
(CONTROL AND STATUS
READBACK)
÷2 ×2
SYSTEM
CLOCK PFD/CP ÷N3
MULTIPLIER
LF
RF
DIVIDER 1
÷3 TO ÷11
MAX 1.25GHz
÷M0
FRAME SYNC
MODE ONLY
÷M1
÷2
÷2
÷2
REF MONITORING
AUTOMATIC
SWITCHING
AD9558
R DIVIDER
(20-BIT)
17-BIT
INTEGER
÷N1
FRAC1/
MOD1
DPFD
24b/24b
RESOLUTION
FREE RUN
TW
DIGITAL
LOOP
FILTER
TUNING
WORD
CLAMP
AND
HISTORY
DIGITAL PLL (DPLL)
2kHz TO 8kHz FRAME SYNC SIGNAL
×2
30-BIT
NCO
RF
DIVIDER 2
÷3 TO ÷11
FRAME SYNC PULSE
÷M2
÷M3
÷M3b
×2
÷N2
OUTPUT PLL (APLL)
PFD/CP LF
3.35GHz
TO
4.05GHz
APLL
STATUS
LF_VCO2
OUT0¹
OUT0¹
OUT1¹
OUT1¹
OUT2¹
OUT2¹
OUT3¹
OUT3¹
OUT4¹
OUT4¹
OUT5¹
OUT5¹
1_{OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.25GHz; OUT5: 352Hz TO 1.25GHz}
Figure 35. Detailed Block Diagram
OVERVIEW
The AD9558 provides clocking outputs that are directly related
in phase and frequency to the selected (active) reference, but
with jitter characteristics that are governed by the system clock,
the DCO, and the output PLL (APLL). The AD9558 supports
up to four reference inputs and input frequencies ranging from
2 kHz to 1250 MHz. The core of this product is a digital phase-
locked loop (DPLL). The DPLL has a programmable digital loop
filter that greatly reduces jitter that is transferred from the active
reference to the output. The AD9558 supports both manual and
automatic holdover. While in holdover, the AD9558 continues to
provide an output as long as the system clock is present. The
holdover output frequency is a time average of the output
frequency history just prior to the transition to the holdover
condition. The device offers manual and automatic reference
switchover capability if the active reference is degraded or fails
completely. The AD9558 also has adaptive clocking capability
that allows the DPLL divider ratios to be changed while the DPLL
is locked.
The AD9558 has a system clock multiplier, a digital PLL (DPLL),
and an analog PLL (APLL). The input signal goes first to the DPLL,
which performs the jitter cleaning and most of the frequency
translation. The DPLL features a 30-bit digitally controlled
oscillator (DCO) output that generates a signal in the 175 MHz
to 200 MHz range. The DPLL output goes to an analog integer-N
PLL (APLL), which multiplies the signal up to the 3.35 GHz to
4.05 GHz range. That signal is then sent to the clock distribution
section, which has two divide-by-3 to divide-by-11 RF dividers
that are cascaded with 10-bit integer (divide-by-1 to divide-by-
1024) channel dividers.
The XOA and XOB pins provide the input for the system clock.
These pins accept a reference clock in the 10 MHz to 600 MHz
range, or a 10 MHz to 50 MHz crystal connected directly across
the XOA and XOB pins. The system clock provides the clocks to
the frequency monitors, the DPLL, and internal switching logic.
The AD9558 has six output drivers, arranged into four channels.
Each channel has a dedicated 10-bit programmable post divider.
Channel 0 and Channel 3 have one driver each, and Channel 1
and Channel 2 have two drivers each. Each driver is programmable
either as a single differential or dual single-ended CMOS output.
The clock distribution section operates at up to 1250 MHz.
In differential mode, the output drivers run on a 1.8 V power
supply to offer very high performance with minimal power
consumption. There are two differential modes: LVDS and 1.8 V
HSTL. In 1.8 V HSTL mode, the voltage swing is compatible
with LVPECL. If LVPECL signal levels are required, the designer
can ac-couple the AD9558 output and use Thevenin-equivalent
termination at the destination to drive the LVPECL inputs.
In single-ended mode, each differential output driver can
operate as two single-ended CMOS outputs. OUT0 and OUT5
support either 1.8 V or 3.3 V CMOS operation. OUT1 through
OUT4 support only 1.8 V operation.
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