AD9558 Datasheet, PDF (37/104 Pages) Analog Devices – Quad Input Multiservice Line Card Adaptive

Data Sheet
OUTPUT PLL (APLL)
A diagram of the output PLL (APLL) is shown in Figure 39.
INTEGER DIVIDER
÷N2
OUTPUT PLL DIVIDER (APLL)
FROM DPLL
PFD
CP
LF
TO CLOCK
VCO2
DISTRIBUTION
3.35GHz TO 4.05GHz
LF_VCO2
LF CAP
Figure 39. Output PLL Block Diagram
The APLL provides the frequency upconversion from the DPLL
output to the 3.35 GHz to 4.05 GHz range, while also providing
noise filtering on the DPLL output. The APLL reference input is
the output of the DPLL. The feedback divider is an integer divider.
The loop filter is partially integrated with the one external 6.8 nF
capacitor. The nominal loop bandwidth for this PLL is 250 kHz,
with 68 degrees of phase margin.
The frequency wizard that is included in the evaluation software
configures the APLL, and the user should not need to make
changes to the APLL settings. However, there may be special cases
where the user may wish to adjust the APLL loop bandwidth to
meet a specific phase noise requirement. The easiest way to change
the APLL loop BW is to adjust the APLL charge pump current
in Register 0x0400. There is sufficient stability (680 of phase
margin) in the APLL default settings to permit a broad range of
adjustment without causing the APLL to be unstable. The user
should contact Analog Devices directly if more detail is needed.
AD9558
Calibration of the APLL must be performed at startup and
when the nominal input frequency to the APLL changes by
more than ±100 ppm, although the APLL maintains lock
over voltage and temperature extremes without recalibration.
Calibration centers the dc operating voltage at the input to the
APLL VCO.
APLL calibration at startup can be accomplished during initial
register loading by following the instructions in the Device
Register Programming When Using a Register Setup File
section of this datasheet.
To recalibrate the APLL VCO after the chip has been running,
the user should first input the new settings (if any). Ensure that
the system clock is still locked and stable, and that the DPLL is
in free run mode with the free run tuning word set to the same
output frequency that is used when the DPLL is locked.
Use the following steps to calibrate the APLL VCO:
1. Ensure that the system clock is locked and stable.
2. Ensure that the DPLL is in user free run mode
(Register 0x0A01[5] = 1b), and the free run tuning word is set.
3. Write Register 0x0405 = 0x20.
4. Write Register 0x0005 = 0x01.
5. Write Register 0x0405 = 0x21.
6. Write Register 0x0005 = 0x01.
Monitor the APLL status using Bit 2 in Register 0x0D01.
Rev. A | Page 37 of 104