AD9558 Datasheet, PDF (25/104 Pages) Analog Devices – Quad Input Multiservice Line Card Adaptive

Data Sheet
AD9558
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
AD9557/
AD9558
HSTL OR
LVDS
100Ω
0.1µF
0.1µF
DOWNSTREAM
DEVICE
WITH HIGH
IMPEDANCE
INPUT AND
INTERNAL
DC BIAS
Figure 30. AC-Coupled LVDS or HSTL Output Driver
(100 Ω resistor can go on either side of decoupling capacitors and should be
as close as possible to the destination receiver.)
10pF
XOA
10MHz TO 50MHz FUNDAMENTAL
AT CUT CRYSTAL WITH
10pF LOAD CAPACITANCE
AD9557/
AD9558
10pF
XOB
Figure 33. System Clock Input (XOA, XOB) in Crystal Mode
(The recommended CLOAD = 10 pF is shown. The values of the 10 pF shunt
capacitors shown here should equal the CLOAD of the crystal.)
AD9557/
AD9558
HSTL OR
LVDS
Z₀ = 50Ω
SINGLE-ENDED
(NOT COUPLED)
100Ω
Z₀ = 50Ω
LVDS OR 1.8V HSTL
HIGH IMPEDANCE
DIFFERENTIAL
RECEIVER
Figure 31. DC-Coupled LVDS or HSTL Output Driver
V_S = 3.3V
0.1µF
Z₀ = 50Ω ^82Ω
AD9557/
AD9558
1.8V
HSTL
0.1µF
SINGLE-ENDED
(NOT COUPLED)
Z₀ = 50Ω
127Ω
82Ω
3.3V
LVPECL
127Ω
Figure 32. Interfacing the HSTL Driver to a 3.3 V LVPECL Input
(This method incorporates impedance matching and dc biasing for bipolar
LVPECL receivers. If the receiver is self-biased, the termination scheme shown
in Figure 30 is recommended.)
3.3V
CMOS
TCXO
300Ω
0.1µF
150Ω
0.1µF
XOA
AD9557/
AD9558
XOB
Figure 34. System Clock Input (XOA, XOB) When Using a TCXO/OCXO with
3.3 V CMOS Output
Rev. A | Page 25 of 104