AD9558 Datasheet, PDF (79/104 Pages) Analog Devices – Quad Input Multiservice Line Card Adaptive

Data Sheet
AD9558
Table 63. Base Digital Loop Filter with Normal Phase Margin (PM = 70°, BW = 0.1 Hz, Third Pole Frequency = 2 Hz, N1 = 1)¹
Address Bits Bit Name
Description
0x0323 [7:0] NPM Alpha-0 linear
Alpha-0 coefficient linear, Bits[7:0]
0x0324 [7:0]
Alpha-0 coefficient linear, Bits[15:8]
0x0325 7
Reserved
Reserved
[6:0] NPM Alpha-1 exponent Alpha-1 coefficient exponent, Bits[6:0]
0x0326 [7:0] NPM Beta-0 linear
Beta-0 coefficient linear, Bits[7:0]
0x0327 [7:0]
Beta-0 coefficient linear, Bits[15:8]
0x0328 7
Reserved
Reserved
[6:0] NPM Beta-1 exponent
Beta-1 coefficient exponent, Bits[6:0]
0x0329 [7:0] NPM Gamma-0 linear
Gamma-0 coefficient linear, Bits[7:0]
0x032A [7:0]
Gamma-0 coefficient linear, Bits[15:8]
0x032B 7
Reserved
Reserved
[6:0] NPM Gamma-1 exponent Gamma-1 coefficient exponent, Bits[6:0]
0x032C [7:0] NPM Delta-0 linear
Delta-0 coefficient linear, Bits[7:0]
0x032D [7:0]
Delta-0 coefficient linear, Bits[15:8]
0x032E 7
Reserved
Reserved
[6:0] NPM Delta-1 exponent
Delta-1 coefficient exponent, Bits[6:0]
1 _{Note that the digital loop filter base coefficients (α, β, γ, and δ) have the following general form: x(2}y_{), where x is the linear component and y is the exponential}
component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 ≤ x ≤ 1. The exponential component (y) is a signed integer.
OUTPUT PLL CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0408)
Table 64. Output PLL Setting¹
Address Bits Bit Name
0x0400
[7:0] Output PLL (APLL)
charge pump current
0x0401 [7:0] APLL N divider
0x0402
0x0403
[7:0] Reserved
[7:6] APLL loop filter control
[5:3]
Description
LSB = 3.5 μA
00000001b = 1 × LSB; 00000010b = 2 × LSB; 11111111b = 255 × LSB
Default: 0x81 = 451 μA CP current
Division = 14 to 255
Default: 0x14 = divide-by-20
Reserved; default: 0x00
Pole 2 resistor Rp2; default: 0x07
Rp2 (Ω)
Bit 7
Bit 6
500 (default)
0
0
333
0
1
250
1
0
200
1
1
Zero resistor, Rzero
Rzero (Ω)
Bit 5
Bit 4
Bit 3
1500 (default)
0
0
0
1250
0
0
1
1000
0
1
0
930
0
1
1
1250
1
0
0
1000
1
0
1
750
1
1
0
680
1
1
1
Rev. A | Page 79 of 104