ADSP-BF608BBCZ-5 Datasheet, PDF (85/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 52 and Figure 36 describe SPI port slave operations. Note
that:
• In dual mode data transmit the SPI_MOSI signal is also an
output.
• In quad mode data transmit the SPI_MOSI, SPI_D2, and
SPI_D3 signals are also outputs.
Table 52. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t_SPICHS
SPI_CLK High Period for Data Transmit¹
SPI_CLK High Period for Data Receive¹
t_SPICLS
t_SPICLK
SPI_CLK Low Period for Data Transmit¹
SPI_CLK Low Period for Data Receive¹
SPI_CLK Period for Data Transmit¹
SPI_CLK Period for Data Receive¹
t_HDS
Last SPI_CLK Edge to SPI_SS Not Asserted
t_SPITDS
Sequential Transfer Delay
t_SDSCI
SPI_SS Assertion to First SPI_CLK Edge
t_SSPID
Data Input Valid to SPI_CLK Edge (Data Input Setup)
t_HSPID
SPI_CLK Sampling Edge to Data Input Invalid
Switching Characteristics
t_DSOE
t_DSDHI
t_DDSPID
t_HDSPID
SPI_SS Assertion to Data Out Active
SPI_SS Deassertion to Data High Impedance
SPI_CLK Edge to Data Out Valid (Data Out Delay)
SPI_CLK Edge to Data Out Invalid (Data Out Hold)
1 _{Whichever is greater.}
• In dual mode data receive the SPI_MISO signal is also an
input.
• In quad mode data receive the SPI_MISO, SPI_D2, and
SPI_D3 signals are also inputs.
V_{DD_EXT}
1.8 V/3.3 V Nominal
Min
Max
[0.5 × t_SCLK1 – 1.5] or [7.0]
[0.5 × t_SCLK1 – 1.5] or [4.5]
[0.5 × t_SCLK1 – 1.5] or [7.0]
[0.5 × t_SCLK1 – 1.5] or [4.5]
[t_SCLK1 – 1.5] or [17]
[t_SCLK1 – 1.5] or [12]
5
0.5 × t_SPICLK – 1.5
10.5
2.0
1.6
0
14
0
12.5
14
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 85 of 112 | June 2013