ADSP-BF608BBCZ-5 Datasheet, PDF (68/112 Pages) Analog Devices – Blackfin Dual Core Embedded Processor

ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DDR2 SDRAM Read Cycle Timing
Table 37. DDR2 SDRAM Read Cycle Timing, V_{DD_DMC} Nominal 1.8 V
Parameter
Min
Timing Requirements
t_DV
Data Valid Window
1
t_DQSQ
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_
DQ Signals
t_QH
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS
1.6
t_RPRE
Read Preamble
0.9
t_RPST
Read Postamble
0.4
1 _{In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.}
250 MHz¹
Max
0.35
DDR2_CLKx
DDR2_CLKx
DDR2_ADDR
DDR2_CTL
DDR2_DQSn
DDR2_DQSn
DDR2_DATA
t_CK
t_CH
t_CL
t_AS
t_AH
t_AC
t_RPRE
t_DQSCK
t_DQSQ
t_QH
t_DQSQ
t_RPST
t_QH
Figure 20. DDR2 SDRAM Controller Input AC Timing
Unit
ns
ns
ns
t_CK
t_CK
Rev. 0 | Page 68 of 112 | June 2013